From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BD6E60DDC; Wed, 6 Mar 2024 09:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709718221; cv=none; b=uh81pJEZdk75Rn23CZazporG/AXQ/QXw5DvIDwTCiUfFKO1g3UMolPt2rngneW/04PJ2higR8EMwMn436gDEKMCCHse1WnC3I8NwDHNYdJ6DtRYKA4/WdpF0mRb0nXYdeyODvIfwAMfWvjEup9wzA7VVrvC+rzNNeMotfMxSvTU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709718221; c=relaxed/simple; bh=VlacLIJetZbSc37w9oCgwWXUQ4SkJoVFKp/+32psVko=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=UAvUc/vfH/S2TetZWw6EHCt9UVpBeFP+8xPms2nDwC2vLi1YzPMweytbcjvGy4uJ2OEbLJIhek/k35tmUs22v1p+oiKalrG/oB6/wSw/KpJc6X0fQ2ZKhEXmziFhr+Z8Ua0mL3f+FHBydTNaazYEk2dxjLWuGOpcq5jeq6grx38= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PNyDIZhd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PNyDIZhd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD56FC433C7; Wed, 6 Mar 2024 09:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709718220; bh=VlacLIJetZbSc37w9oCgwWXUQ4SkJoVFKp/+32psVko=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PNyDIZhdO1Map2G6d312fQ+R4uj7Oko/SG1vXb/T+mcs7mNxUFEfjumYvZB2nbFSc OgDu5OKOhDlr3Yx4uEzDy1/3uL3ntEGBau1Gs9j6O5dZ3mUDhqq5oJy61RwaxOUlPB q/rlFlsav4ajiR52rEpi3CVXmDOFfMpmNg6ZrBVF1O2GIhfTe/mY/EVK/CGfFTFI/8 C5PhcaHrax6zprup1/lXjqwgrtXle+FgxSKWUTQCjKh+XsQnoYdgsCFvhYNAFo6tKw ArMgHNAqTcoTKfusv6a/ak7ffy9Y7kzrwFUtKn1AXk1JfvrtOjzda4yRVLF8QGXTvf hj7YRdmDj2BwA== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rhnoH-009sbl-1f; Wed, 06 Mar 2024 09:43:38 +0000 Date: Wed, 06 Mar 2024 09:43:13 +0000 Message-ID: <87edcnr8zy.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , James Clark , Anshuman Khandual Subject: Re: [PATCH 5/5] KVM: arm64: Exclude FP ownership from kvm_vcpu_arch In-Reply-To: <6acffbef-6872-4a15-b24a-7a0ec6bbb373@sirena.org.uk> References: <20240302111935.129994-1-maz@kernel.org> <20240302111935.129994-6-maz@kernel.org> <6acffbef-6872-4a15-b24a-7a0ec6bbb373@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: broonie@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, james.clark@arm.com, anshuman.khandual@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 04 Mar 2024 19:10:08 +0000, Mark Brown wrote: > > [1 ] > On Sat, Mar 02, 2024 at 11:19:35AM +0000, Marc Zyngier wrote: > > In retrospect, it is fairly obvious that the FP state ownership > > is only meaningful for a given CPU, and that locating this > > information in the vcpu was just a mistake. > > > > Move the ownership tracking into the host data structure, and > > rename it from fp_state to fp_owner, which is a better description > > (name suggested by Mark Brown). > > The SME patch series proposes adding an additional state to this > enumeration which would say if the registers are stored in a format > suitable for exchange with userspace, that would make this state part of > the vCPU state. With the addition of SME we can have two vector lengths > in play so the series proposes picking the larger to be the format for > userspace registers. What does this addition have anything to do with the ownership of the physical register file? Not a lot, it seems. Specially as there better be no state resident on the CPU when userspace messes up with it. > > We could store this separately to fp_state/owner but it'd still be a > value stored in the vCPU. I totally disagree. > Storing in a format suitable for userspace > usage all the time when we've got SME would most likely result in > performance overhead What performance overhead? Why should we care? > if nothing else and feels more complicated than > rewriting the data in the relatively unusual case where userspace looks > at it. Trying to convert userspace writes into the current layout would > have issues if the current layout uses the smaller vector length and > create fragility with ordering issues when loading the guest state. What ordering issues? If userspace manipulates the guest state, the guest isn't running. If it is, all bets are off. > > The proposal is not the most lovely idea ever but given the architecture > I think some degree of clunkiness would be unavoidable. It is only unavoidable if we decide to make a bad job of it. M. -- Without deviation from the norm, progress is not possible.