From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17321C432BE for ; Wed, 18 Aug 2021 15:16:16 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 7E5DE6104F for ; Wed, 18 Aug 2021 15:16:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7E5DE6104F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 1B8D740617; Wed, 18 Aug 2021 11:16:15 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GspcoVleVidr; Wed, 18 Aug 2021 11:16:09 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id EB79B4A1A5; Wed, 18 Aug 2021 11:16:09 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 206774B0E1 for ; Wed, 18 Aug 2021 11:16:09 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 39jdTn6rzZ90 for ; Wed, 18 Aug 2021 11:16:08 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id E10B04A1B0 for ; Wed, 18 Aug 2021 11:16:07 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E8BE961042; Wed, 18 Aug 2021 15:16:06 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mGNIS-005mkS-Rq; Wed, 18 Aug 2021 16:16:05 +0100 Date: Wed, 18 Aug 2021 16:16:04 +0100 Message-ID: <87h7fmss0b.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Subject: Re: [PATCH v4 10/15] KVM: arm64: Add config register bit definitions In-Reply-To: <20210817081134.2918285-11-tabba@google.com> References: <20210817081134.2918285-1-tabba@google.com> <20210817081134.2918285-11-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.cs.columbia.edu, will@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, pbonzini@redhat.com, drjones@redhat.com, oupton@google.com, qperret@google.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kernel-team@android.com, kvm@vger.kernel.org, pbonzini@redhat.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Tue, 17 Aug 2021 09:11:29 +0100, Fuad Tabba wrote: > > Add hardware configuration register bit definitions for HCR_EL2 > and MDCR_EL2. Future patches toggle these hyp configuration > register bits to trap on certain accesses. > > No functional change intended. > > Acked-by: Will Deacon > Signed-off-by: Fuad Tabba > --- > arch/arm64/include/asm/kvm_arm.h | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index a928b2dc0b0f..327120c0089f 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -12,8 +12,13 @@ > #include > > /* Hyp Configuration Register (HCR) bits */ > + > +#define HCR_TID5 (UL(1) << 58) > +#define HCR_DCT (UL(1) << 57) > #define HCR_ATA_SHIFT 56 > #define HCR_ATA (UL(1) << HCR_ATA_SHIFT) > +#define HCR_AMVOFFEN (UL(1) << 51) > +#define HCR_FIEN (UL(1) << 47) > #define HCR_FWB (UL(1) << 46) > #define HCR_API (UL(1) << 41) > #define HCR_APK (UL(1) << 40) > @@ -56,6 +61,7 @@ > #define HCR_PTW (UL(1) << 2) > #define HCR_SWIO (UL(1) << 1) > #define HCR_VM (UL(1) << 0) > +#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39)) > > /* > * The bits we set in HCR: > @@ -277,11 +283,21 @@ > #define CPTR_EL2_TZ (1 << 8) > #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ > #define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1 > +#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \ > + GENMASK(29, 21) | \ > + GENMASK(19, 14) | \ > + BIT(11)) > > /* Hyp Debug Configuration Register bits */ > #define MDCR_EL2_E2TB_MASK (UL(0x3)) > #define MDCR_EL2_E2TB_SHIFT (UL(24)) > +#define MDCR_EL2_HPMFZS (UL(1) << 36) > +#define MDCR_EL2_HPMFZO (UL(1) << 29) > +#define MDCR_EL2_MTPME (UL(1) << 28) > +#define MDCR_EL2_TDCC (UL(1) << 27) > +#define MDCR_EL2_HCCD (UL(1) << 23) Nit: If you're aiming for completeness, you're missing MDCR_EL2.HLP (bit 26). > #define MDCR_EL2_TTRF (UL(1) << 19) > +#define MDCR_EL2_HPMD (UL(1) << 17) > #define MDCR_EL2_TPMS (UL(1) << 14) > #define MDCR_EL2_E2PB_MASK (UL(0x3)) > #define MDCR_EL2_E2PB_SHIFT (UL(12)) > @@ -293,6 +309,12 @@ > #define MDCR_EL2_TPM (UL(1) << 6) > #define MDCR_EL2_TPMCR (UL(1) << 5) > #define MDCR_EL2_HPMN_MASK (UL(0x1F)) > +#define MDCR_EL2_RES0 (GENMASK(63, 37) | \ > + GENMASK(35, 30) | \ > + GENMASK(25, 24) | \ > + GENMASK(22, 20) | \ > + BIT(18) | \ > + GENMASK(16, 15)) > > /* For compatibility with fault code shared with 32-bit */ > #define FSC_FAULT ESR_ELx_FSC_FAULT Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm