From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3A90286880 for ; Fri, 6 Jun 2025 09:53:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749203606; cv=none; b=p8sVlHJUlRUkoJy5WJ9SGWLOmeRIhlpnIkragT1YPgky0MCQy7gmIBtdtXzf6KgKUee1w/YmMqr9ukgl7zQJJPf8cXPR1vNgG4mTmwc06UY7IfPbT6UPpSg3eWjt9SQn4NYPQyWsOB7gI88EqqtuobgSzE/dbqimAO7c9QIbo38= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749203606; c=relaxed/simple; bh=caDhiznchzQE+mh1NFtjsVc4MpjBfZRuA3b7zuJEJZo=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=Ux86ttkCI4ImkND2RUDmQmMH76nRtbqIG2EPaSjjogFg8Pppxib3QfNSD5yH1PMDISbG5K3MbUE3wsSxVNvc/NuskUAn7vzWb+8XMQFk9Mjw01t3x/B7y/04YXxxbspmL6edARk9Nba/iqrAoGvCSIu8dZLhO5PcTrpDWBboXs4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=ODJEFLEO; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="ODJEFLEO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749203603; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=587k/XgzXZDVRc17FBl8LYWYXXgKDx/cGubX/1kvN5I=; b=ODJEFLEOXyi0qNuxD9r5yY5wKamq6bTxdqXqYI5ZR/eLKuWivgk230yRGSb2ulB/ff2sXx R6zeM4zjYVhoWRDjB+U5jReb13fx6cGZZqa2fAQwiIG3xYXyc6IhEkb9IlmG0KE3aCiHSL gwDLWk7UViKRWxgHGoX9HXct+HbHYBs= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-460-35AzavJdMMC8zE3OqGrBDA-1; Fri, 06 Jun 2025 05:53:22 -0400 X-MC-Unique: 35AzavJdMMC8zE3OqGrBDA-1 X-Mimecast-MFC-AGG-ID: 35AzavJdMMC8zE3OqGrBDA_1749203600 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 935931956080; Fri, 6 Jun 2025 09:53:19 +0000 (UTC) Received: from localhost (dhcp-192-175.str.redhat.com [10.33.192.175]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id DEF23180035E; Fri, 6 Jun 2025 09:53:17 +0000 (UTC) From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [PATCH v7 00/14] arm: rework id register storage In-Reply-To: <20250515153907.151174-1-cohuck@redhat.com> Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Michael O'Neill, Amy Ross" References: <20250515153907.151174-1-cohuck@redhat.com> User-Agent: Notmuch/0.38.3 (https://notmuchmail.org) Date: Fri, 06 Jun 2025 11:53:15 +0200 Message-ID: <87ikl99oxg.fsf@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Friendly ping... anything else that needs to happen here? On Thu, May 15 2025, Cornelia Huck wrote: > Some small fixes, including fixing up/adding SPDX identifiers, keeping the > series bisectable, and updating MAINTAINERS (please check if that's ok.) > > Also available at > https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v7 > > > Just some small changes: > - fixed up some botched conversions noted by Eric (thanks!) > - rebased to current master > - new patch with a small cleanup suggested by Eric > > > Just a quick respin to fix a missed conversion in hvf.c. > > > Next iteration of the id register patches; only small changes. > > Changed from v3: > - added R-bs (thanks!) > - added missing SPDX header > - merged patch introducing accessors for kvm to the first user > - skip over sysregs outside of the id register range when generating > register definitions again > > Also available at > https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v4 > > > Yet another update of the id register series, less changes this time > around. > > Changed from v2: > - changed generation of the various register defines via the "DEF" > magic suggested by Richard > - some kvm-only code moved to kvm.c; some code potentially useful to > non-kvm code stayed out of there (the cpu model code will make use > of it, and that one should be extendable outside of kvm -- a > revised version of those patches is still in the works, but I'll be > off for a few days and rather wanted to get this one out first) > > Also available at > https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v3 > > > > Changed from v1: > - Noticed that we missed the hvf code. Converted, compiled, but not tested > as I'm lacking an environment for testing. > - Hopefully incorporated most of the suggested changes -- if I missed > something, it was unintentional unless mentioned below. > - fixed repeated inclusion of definitions > - hopefully made macros more robust > - removed distinction between reading 32/64 values, which was mostly > adding churn for little value > - postponed generating property definitions to the cpu model patches, > where they are actually used > - juggled hunks and moved them to the right patches > - fixed some typos > - rebased to a more recent code base > > NOT changed from v1: > - definitions are still generated from the Linux sysregs file > - I still think updating the generated files on demand (so that we can > double check the result) is the right thing to do > - I'm open to changing the source of the definitions from the sysregs > file to the JSON definitions published by Arm; however, I first wanted > to get the code using it right -- we can switch out the code generating > the file to use a different source easily later on, and I'd also like > to steal parts of the script from Linux once integrated (which I think > hasn't happened yet?) > > > > [Note: I've kept the cc list from the last round of cpu model patches; > so if you're confused as to why you're cc:ed here, take it as a > heads-up that a new cpu model series will come along soon] > > This patch series contains patches extracted from the larger cpu model > series (RFC v2 last posted at > https://lore.kernel.org/qemu-devel/20241206112213.88394-1-cohuck@redhat.com/) > and aims at providing a base upon which we can continue with building > support for cpu models, but which is hopefully already an improvement > on its own. > > Main changes from the patches in that series include: > - post-pone the changes to handle KVM writable ID registers for cpu models > (I have a series including that on top of this one) > - change how we store the list of ID registers, and access them > basically, use an enum for indexing, and an enum doing encodings in a > pattern similar to cpregs > - move some hunks to different patches > - update the scripts to generate the register descriptions, and run > them against a recent Linux sysregs file > > What I've kept: > - generating the register descriptions from the Linux sysregs file > I think that file is still our best bet to generate the descriptions > easily, and updating the definitions is a manual step that can be checked > for unintended changes > - most of the hard work that Eric had been doing; all new bugs in there > are my own :) > > > > > > > > > Cornelia Huck (2): > arm/cpu: switch to a generated cpu-sysregs.h.inc > arm/kvm: use fd instead of fdarray[2] > > Eric Auger (12): > arm/cpu: Add sysreg definitions in cpu-sysregs.h > arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays > arm/cpu: Store aa64isar1/2 into the idregs array > arm/cpu: Store aa64pfr0/1 into the idregs array > arm/cpu: Store aa64mmfr0-3 into the idregs array > arm/cpu: Store aa64dfr0/1 into the idregs array > arm/cpu: Store aa64smfr0 into the idregs array > arm/cpu: Store id_isar0-7 into the idregs array > arm/cpu: Store id_pfr0/1/2 into the idregs array > arm/cpu: Store id_dfr0/1 into the idregs array > arm/cpu: Store id_mmfr0-5 into the idregs array > arm/cpu: Add sysreg generation scripts > > MAINTAINERS | 1 + > hw/intc/armv7m_nvic.c | 27 +- > scripts/gen-cpu-sysregs-header.awk | 35 ++ > scripts/update-aarch64-sysreg-code.sh | 26 ++ > target/arm/cpu-features.h | 317 +++++++++--------- > target/arm/cpu-sysregs.h | 42 +++ > target/arm/cpu-sysregs.h.inc | 52 +++ > target/arm/cpu.c | 111 +++---- > target/arm/cpu.h | 80 +++-- > target/arm/cpu64.c | 128 +++---- > target/arm/helper.c | 68 ++-- > target/arm/hvf/hvf.c | 39 ++- > target/arm/internals.h | 6 +- > target/arm/kvm.c | 139 ++++---- > target/arm/ptw.c | 6 +- > target/arm/tcg/cpu-v7m.c | 174 +++++----- > target/arm/tcg/cpu32.c | 320 +++++++++--------- > target/arm/tcg/cpu64.c | 459 +++++++++++++------------- > 18 files changed, 1105 insertions(+), 925 deletions(-) > create mode 100755 scripts/gen-cpu-sysregs-header.awk > create mode 100755 scripts/update-aarch64-sysreg-code.sh > create mode 100644 target/arm/cpu-sysregs.h > create mode 100644 target/arm/cpu-sysregs.h.inc > > -- > 2.49.0