From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B7BDC433F5 for ; Fri, 29 Oct 2021 11:17:05 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 20A4E61056 for ; Fri, 29 Oct 2021 11:17:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 20A4E61056 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A5B884B190; Fri, 29 Oct 2021 07:17:04 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id B7wub4F9lZd8; Fri, 29 Oct 2021 07:17:03 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 28A6B4B12E; Fri, 29 Oct 2021 07:17:03 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id BA6324B126 for ; Fri, 29 Oct 2021 07:17:01 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FJpBRj9NkqEp for ; Fri, 29 Oct 2021 07:17:00 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 2FE374B125 for ; Fri, 29 Oct 2021 07:17:00 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 22FC0610D2; Fri, 29 Oct 2021 11:16:59 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mgPsW-002Ow6-VI; Fri, 29 Oct 2021 12:16:57 +0100 Date: Fri, 29 Oct 2021 12:16:56 +0100 Message-ID: <87mtms9j2v.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Subject: Re: [PATCH 2/3] KVM: arm64: Allow the guest to change the OS Lock status In-Reply-To: <20211029003202.158161-3-oupton@google.com> References: <20211029003202.158161-1-oupton@google.com> <20211029003202.158161-3-oupton@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@google.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, drjones@redhat.com, pshier@google.com, ricarkol@google.com, reijiw@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Peter Shier , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Oliver, On Fri, 29 Oct 2021 01:32:01 +0100, Oliver Upton wrote: > > KVM diverges from the architecture in the way it handles the OSLAR_EL1 > register. While the architecture requires that the register be WO and > that the OSLK bit is 1 out of reset, KVM implements the register as > RAZ/WI. > > Align KVM with the architecture by permitting writes to OSLAR_EL1. Since > the register is WO, stash the OS Lock status bit in OSLSR_EL1 and > context switch the status between host/guest. Additionally, change the > reset value of the OSLK bit to 1. > > Suggested-by: Marc Zyngier > Signed-off-by: Oliver Upton > --- > arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 5 +++++ > arch/arm64/kvm/sys_regs.c | 22 +++++++++++++++++++--- > 2 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h > index de7e14c862e6..a65dab34f85b 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h > +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h > @@ -65,6 +65,8 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) > ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1); > ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR); > ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR); > + > + ctxt_sys_reg(ctxt, OSLSR_EL1) = read_sysreg(oslsr_el1); Why do we need to save/restore this outside of the debug context? It seems to me that this is only needed if debug has been enabled by the guest (KVM_ARM64_DEBUG_DIRTY being set), as we will have trapped the OSLAR_EL1 access otherwise. I don't think we need to deal with this register outside of this context, as debug exceptions cannot happen otherwise (BRK excepted, of course). > } > > static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt) > @@ -149,6 +151,9 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) > write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1); > write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR); > write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR); > + > + /* restore OSLSR_EL1 by writing the OSLK bit to OSLAR_EL1 */ > + write_sysreg((ctxt_sys_reg(ctxt, OSLSR_EL1) >> 1) & 1, oslar_el1); Please introduce some eye-pleasing bit definitions ("Here, there, and everywhere", to quote someone famous). > } > > static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt) > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 0eb03e7508fe..0840ae081290 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -298,6 +298,22 @@ static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, > return true; > } > > +static bool trap_oslar_el1(struct kvm_vcpu *vcpu, > + struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 oslsr; > + > + if (!p->is_write) > + return read_zero(vcpu, p); This really should be an UNDEF (and it really should UNDEF in HW, but we are being, maybe pointlessly, cautious). > + > + /* preserve all but the OSLK bit */ > + oslsr = vcpu_read_sys_reg(vcpu, OSLSR_EL1) & ~0x2ull; > + vcpu_write_sys_reg(vcpu, OSLSR_EL1, oslsr | ((p->regval & 1) << 1)); > + return true; > +} > + > + Extra newline. > static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, > struct sys_reg_params *p, > const struct sys_reg_desc *r) > @@ -1439,8 +1455,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { > DBG_BCR_BVR_WCR_WVR_EL1(15), > > { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, > - { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, > - { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x00000008 }, > + { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, > + { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 0x0000000A }, > { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, > { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, > { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, > @@ -1912,7 +1928,7 @@ static const struct sys_reg_desc cp14_regs[] = { > > DBGBXVR(0), > /* DBGOSLAR */ > - { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, > + { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, > DBGBXVR(1), > /* DBGOSLSR */ > { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm