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Thu, 17 Jun 2021 08:44:51 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ltndp-0088M1-Ph; Thu, 17 Jun 2021 09:44:49 +0100 Date: Thu, 17 Jun 2021 09:44:49 +0100 Message-ID: <87mtrodgn2.wl-maz@kernel.org> From: Marc Zyngier To: "wangyanan (Y)" Subject: Re: [PATCH v6 1/4] KVM: arm64: Introduce cache maintenance callbacks for guest stage-2 In-Reply-To: <0dced974-b507-ce48-b89d-344d41a02418@huawei.com> References: <20210616095200.38008-1-wangyanan55@huawei.com> <20210616095200.38008-2-wangyanan55@huawei.com> <87eed2lzcc.wl-maz@kernel.org> <8340be12-cc80-8c2a-3597-ecba05eaf35a@huawei.com> <87o8c4dikn.wl-maz@kernel.org> <0dced974-b507-ce48-b89d-344d41a02418@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: wangyanan55@huawei.com, will@kernel.org, qperret@google.com, alexandru.elisei@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, gshan@redhat.com, wanghaibin.wang@huawei.com, zhukeqian1@huawei.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Will Deacon , linux-kernel@vger.kernel.org, Catalin Marinas , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, 17 Jun 2021 09:22:51 +0100, "wangyanan (Y)" wrote: > > > > On 2021/6/17 16:03, Marc Zyngier wrote: > > On Thu, 17 Jun 2021 07:48:29 +0100, > > "wangyanan (Y)" wrote: > >> Hi Marc, > >> > >> On 2021/6/16 21:21, Marc Zyngier wrote: > >>> Hi Yanan, > >>> > >>> On Wed, 16 Jun 2021 10:51:57 +0100, > >>> Yanan Wang wrote: > >>>> To prepare for performing guest CMOs in the fault handlers in pgtable.c, > >>>> introduce two cache maintenance callbacks in struct kvm_pgtable_mm_ops. > >>>> > >>>> The new callbacks are specific for guest stage-2, so they will only be > >>>> initialized in 'struct kvm_pgtable_mm_ops kvm_s2_mm_ops'. > >>>> > >>>> Signed-off-by: Yanan Wang > >>>> --- > >>>> arch/arm64/include/asm/kvm_pgtable.h | 7 +++++++ > >>>> 1 file changed, 7 insertions(+) > >>>> > >>>> diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > >>>> index c3674c47d48c..302eca32e0af 100644 > >>>> --- a/arch/arm64/include/asm/kvm_pgtable.h > >>>> +++ b/arch/arm64/include/asm/kvm_pgtable.h > >>>> @@ -44,6 +44,11 @@ typedef u64 kvm_pte_t; > >>>> * in the current context. > >>>> * @virt_to_phys: Convert a virtual address mapped in the current context > >>>> * into a physical address. > >>>> + * @flush_dcache: Clean data cache for a guest page address range before > >>>> + * creating the corresponding stage-2 mapping. > >>> Please don't reintroduce the word 'flush'. We are really trying to > >>> move away from it as it doesn't describe what we want to do. > >> I agree with this. I intended to make the names short and laconic, but this > >> missed the information about the callback's actual behaviors. > >>> Here this > >>> should be 'clean_invalidate_dcache' which, despite being a mouthful, > >>> describe accurately what we expect it to do. > >> Sure, I will change the name as you suggested. > >>> The comment is also missing the invalidate part, and we shouldn't > >>> assume that this is only used for S2 mapping. > >> Ok, will refine the comment. I think something like"Clean and invalidate the > >> date cache for the specified memory address range" may be generic enough. > >>>> + * @flush_icache: Invalidate instruction cache for a guest page address > >>>> + * range before creating or updating the corresponding > >>>> + * stage-2 mapping. > >>> Same thing here; this should be 'invalidate_icache', and the comment > >>> cleaned up. > >> Thanks, I will also correct this part. > >> > >> Besides the callback names and comments, is there anything else that still > >> needs some adjustment in the other three patches? :) > > It looks pretty good so far, much nicer than the previous versions. > > > > I have a small nit on the last patch, which should be dead easy to > > address. I'm currently running a bunch of tests, hopefully nothing bad > > will come out of it. > > > > If you respin it shortly, that nothing fails, and unless someone > > shouts, I'll queue it for -next. > It would be nice, thanks! > I will address the nit and respin the series soon. By the way, what the status of your selftest series that originally came with this series? Are you planning to respin it? It would be useful to have something that checks for regressions, and that series did seem to do the trick. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm