From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 082F2C4332F for ; Fri, 8 Apr 2022 16:59:58 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7A7574A0FD; Fri, 8 Apr 2022 12:59:58 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@kernel.org Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cDR-OGbvJv2W; Fri, 8 Apr 2022 12:59:57 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3F2474B0EF; Fri, 8 Apr 2022 12:59:57 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3058249EC2 for ; Fri, 8 Apr 2022 12:59:56 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b0x2peNHVuI1 for ; Fri, 8 Apr 2022 12:59:55 -0400 (EDT) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id E25B049EBE for ; Fri, 8 Apr 2022 12:59:54 -0400 (EDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C8CEF62158; Fri, 8 Apr 2022 16:59:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2DA17C385A3; Fri, 8 Apr 2022 16:59:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649437193; bh=hezvIR97K/d6etxHTUv4PJyXJtleS81JAhoNf2K+8hI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=pJvyoIX8LUcDdClF6OFL1/JUuOZNt2xQp37DthOnlJeEXcZ56oLmJkFbQtZwerNyc OhbWw6+aLK6oGjqw6b25PfyzLj/AER9VlLmiAM+LQ/5i8MhbiDdri4zZWMHRT70gZb beYDmMBo+z6TAuKrplYTcbLyPGZ0hxlxcjjCAv4GZcfa7rmmNE0Tm8ScvVtZiDwK0/ HPUz15e3Z+HLPa200pCAwdmPKO8rqplGm8IR0Vt9Qf0SBL+hZjTlKybHoFqlK5ywtl +h7sEDyDqpVv9V7oeXyMTXXtQf9LODvrgCG8l409Qh2jN/UJJskyutVqSOhdcpYZEt bcpiteTImFr1A== Received: from sofa.misterjones.org ([185.219.108.64] helo=billy-the-mountain.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ncrxe-002pMe-Kb; Fri, 08 Apr 2022 17:59:50 +0100 Date: Fri, 08 Apr 2022 17:59:42 +0100 Message-ID: <87v8vj1pfl.wl-maz@kernel.org> From: Marc Zyngier To: Raghavendra Rao Ananta Subject: Re: [PATCH v5 02/10] KVM: arm64: Setup a framework for hypercall bitmap firmware registers In-Reply-To: References: <20220407011605.1966778-1-rananta@google.com> <20220407011605.1966778-3-rananta@google.com> <87ilrlb6un.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: rananta@google.com, drjones@redhat.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, catalin.marinas@arm.com, will@kernel.org, pshier@google.com, ricarkol@google.com, oupton@google.com, reijiw@google.com, jingzhangos@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Will Deacon , Catalin Marinas , Peter Shier , linux-kernel@vger.kernel.org, Paolo Bonzini , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, 07 Apr 2022 18:24:14 +0100, Raghavendra Rao Ananta wrote: > > Hi Marc, > > > > +#define KVM_REG_ARM_STD_BIT_TRNG_V1_0 BIT(0) > > > > I'm really in two minds about this. Having one bit per service is easy > > from an implementation perspective, but is also means that this > > disallow fine grained control over which hypercalls are actually > > available. If tomorrow TRNG 1.1 adds a new hypercall and that KVM > > implements both, how does the selection mechanism works? You will > > need a version selector (a la PSCI), which defeats this API somehow > > (and renders the name of the #define invalid). > > > > I wonder if a more correct way to look at this is to enumerate the > > hypercalls themselves (all 5 of them), though coming up with an > > encoding is tricky (RNG32 and RNG64 would clash, for example). > > > > Thoughts? > > > I was on the fence about this too. The TRNG spec (ARM DEN 0098, > Table-4) mentions that v1.0 should have VERSION, FEATURES, GET_UUID, > and RND as mandatory features. Hence, if KVM advertised that it > supports TRNG v1.0, I thought it would be best to expose all or > nothing of v1.0 by guarding them with a single bit. > Broadly, the idea is to have a bit per version. If v1.1 comes along, > we can have another bit for that. If it's not too ugly to implement, > we can be a little more aggressive and ensure that userspace doesn't > enable v1.1 without enabling v1.0. OK, that'd be assuming that we'll never see a service where version A is incompatible with version B and that we have to exclude one or the other. Meh. Let's cross that bridge once it is actually built. [...] > > > + mutex_lock(&kvm->lock); > > > + > > > + /* > > > + * If the VM (any vCPU) has already started running, return success > > > + * if there's no change in the value. Else, return -EBUSY. > > > > No, this should *always* fail if a vcpu has started. Otherwise, you > > start allowing hard to spot races. > > > The idea came from the fact that userspace could spawn multiple > threads to configure the vCPU registers. Since we don't have the > VM-scoped registers yet, it may be possible that userspace has issued > a KVM_RUN on one of the vCPU, while the others are lagging behind and > still configuring the registers. The slower threads may see -EBUSY and > could panic. But if you feel that it's an overkill and the userspace > should deal with it, we can return EBUSY for all writes after KVM_RUN. I'd rather have that. There already is stuff that rely on things not changing once a vcpu has run, so I'd rather be consistent. > > > > + */ > > > + if (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags)) { > > > + ret = *fw_reg_bmap != val ? -EBUSY : 0; > > > + goto out; > > > + } > > > + > > > + WRITE_ONCE(*fw_reg_bmap, val); > > > > I'm not sure what this WRITE_ONCE guards against. Do you expect > > concurrent reads at this stage? > > > Again, the assumption here is that userspace could have multiple > threads reading and writing to these registers. Without the VM scoped > registers in place, we may end up with a read/write to the same memory > location for all the vCPUs. We only have one vcpu updating this at any given time (that's what the lock ensures). A simple write should be OK, as far as I can tell. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm