From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3CDAC433ED for ; Mon, 10 May 2021 15:05:07 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 0901261421 for ; Mon, 10 May 2021 15:05:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0901261421 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 788F84A483; Mon, 10 May 2021 11:05:06 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yeNDo+N2pL6V; Mon, 10 May 2021 11:05:01 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 45FFD4B32F; Mon, 10 May 2021 11:05:01 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E43A140630 for ; Mon, 10 May 2021 11:04:59 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BSOjVeqNmBpX for ; Mon, 10 May 2021 11:04:58 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 5BD5040CF8 for ; Mon, 10 May 2021 11:04:58 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6DF146147F; Mon, 10 May 2021 15:04:56 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lg7So-000TBy-B7; Mon, 10 May 2021 16:04:54 +0100 Date: Mon, 10 May 2021 16:04:53 +0100 Message-ID: <87v97qociy.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [PATCH 2/2] KVM: arm64: Commit pending PC adjustemnts before returning to userspace In-Reply-To: <7a0f43c8-cc36-810e-0b8e-ffe66672ca82@arm.com> References: <20210510094915.1909484-1-maz@kernel.org> <20210510094915.1909484-3-maz@kernel.org> <7a0f43c8-cc36-810e-0b8e-ffe66672ca82@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, yuzenghui@huawei.com, james.morse@arm.com, suzuki.poulose@arm.com, kernel-team@android.com, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, stable@vger.kernel.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 10 May 2021 15:55:28 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On 5/10/21 10:49 AM, Marc Zyngier wrote: > > KVM currently updates PC (and the corresponding exception state) > > using a two phase approach: first by setting a set of flags, > > then by converting these flags into a state update when the vcpu > > is about to enter the guest. > > > > However, this creates a disconnect with userspace if the vcpu thread > > returns there with any exception/PC flag set. In this case, the exposed > > The code seems to handle only the KVM_ARM64_PENDING_EXCEPTION > flag. Is the "PC flag" a reference to the KVM_ARM64_INCREMENT_PC > flag? No, it does handle both exception and PC increment, unless I have completely bodged something (entirely possible). > > > context is wrong, as userpsace doesn't have access to these flags > > s/userpsace/userspace > > > (they aren't architectural). It also means that these flags are > > preserved across a reset, which isn't expected. > > > > To solve this problem, force an explicit synchronisation of the > > exception state on vcpu exit to userspace. As an optimisation > > for nVHE systems, only perform this when there is something pending. > > > > Reported-by: Zenghui Yu > > Signed-off-by: Marc Zyngier > > Cc: stable@vger.kernel.org # 5.11 > > --- > > arch/arm64/include/asm/kvm_asm.h | 1 + > > arch/arm64/kvm/arm.c | 10 ++++++++++ > > arch/arm64/kvm/hyp/exception.c | 4 ++-- > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 8 ++++++++ > > 4 files changed, 21 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h > > index d5b11037401d..5e9b33cbac51 100644 > > --- a/arch/arm64/include/asm/kvm_asm.h > > +++ b/arch/arm64/include/asm/kvm_asm.h > > @@ -63,6 +63,7 @@ > > #define __KVM_HOST_SMCCC_FUNC___pkvm_cpu_set_vector 18 > > #define __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize 19 > > #define __KVM_HOST_SMCCC_FUNC___pkvm_mark_hyp 20 > > +#define __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc 21 > > > > #ifndef __ASSEMBLY__ > > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > index 1cb39c0803a4..d62a7041ebd1 100644 > > --- a/arch/arm64/kvm/arm.c > > +++ b/arch/arm64/kvm/arm.c > > @@ -897,6 +897,16 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) > > > > kvm_sigset_deactivate(vcpu); > > > > + /* > > + * In the unlikely event that we are returning to userspace > > + * with pending exceptions or PC adjustment, commit these > > I'm going to assume "PC adjustment" means the KVM_ARM64_INCREMENT_PC > flag. Please correct me if that's not true, but if that's the case, > then the flag isn't handled below. > > > + * adjustments in order to give userspace a consistent view of > > + * the vcpu state. > > + */ > > + if (unlikely(vcpu->arch.flags & (KVM_ARM64_PENDING_EXCEPTION | > > + KVM_ARM64_EXCEPT_MASK))) > > The condition seems to suggest that it is valid to set > KVM_ARM64_EXCEPT_{AA32,AA64}_* without setting > KVM_ARM64_PENDING_EXCEPTION, which looks rather odd to me. > Is that a valid use of the KVM_ARM64_EXCEPT_MASK bits? If it's not > (the existing code always sets the exception type with the > KVM_ARM64_PENDING_EXCEPTION), that I was thinking that checking only > the KVM_ARM64_PENDING_EXCEPTION flag would make the intention > clearer. No, you are missing this (subtle) comment in kvm_host.h: /* * Overlaps with KVM_ARM64_EXCEPT_MASK on purpose so that it can't be * set together with an exception... */ #define KVM_ARM64_INCREMENT_PC (1 << 9) /* Increment PC */ So (KVM_ARM64_PENDING_EXCEPTION | KVM_ARM64_EXCEPT_MASK) checks for *both* an exception and a PC increment. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm