From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [PATCH v2 6/6] target-arm: cpu.h document why env->spsr exists Date: Wed, 04 Mar 2015 16:27:29 +0000 Message-ID: <87vbig683y.fsf@linaro.org> References: <1425479753-18349-1-git-send-email-alex.bennee@linaro.org> <1425479753-18349-7-git-send-email-alex.bennee@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-reply-to: Sender: kvm-owner@vger.kernel.org To: Peter Maydell Cc: QEMU Developers , kvm-devel , arm-mail-list , "kvmarm@lists.cs.columbia.edu" , Christoffer Dall , Marc Zyngier List-Id: kvmarm@lists.cs.columbia.edu Peter Maydell writes: > On 4 March 2015 at 23:35, Alex Benn=C3=A9e w= rote: >> I was getting very confused about the duplication of state. Perhaps = we >> should just get rid of env->spsr and use helpers that understand the >> banking? > > Doesn't seem worth changing the current working code to something > else that's strictly less efficient... spsr is by no means the > only banked-by-mode register, and it works just like all the others. =46air enough. I just wanted to make it clear it was a cached value for the benefit of TCG. > > -- PMM --=20 Alex Benn=C3=A9e