From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BC58C433F5 for ; Thu, 27 Jan 2022 12:43:51 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C8CA249F2F; Thu, 27 Jan 2022 07:43:50 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@kernel.org Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I8WmgDMf0Q0V; Thu, 27 Jan 2022 07:43:49 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7B5A449EEB; Thu, 27 Jan 2022 07:43:49 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 5839D49EE1 for ; Thu, 27 Jan 2022 07:43:48 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dnybXp3DcDoG for ; Thu, 27 Jan 2022 07:43:47 -0500 (EST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 2343B49EDE for ; Thu, 27 Jan 2022 07:43:47 -0500 (EST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4F7CB61ABD; Thu, 27 Jan 2022 12:43:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B218AC340E4; Thu, 27 Jan 2022 12:43:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643287425; bh=68fog+LxidxW2xkTBF4OzGMOW1IHoZtRHgu/53kvJ3s=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=XDjYncGb0F3rlAga9c7Y6gNbbK0eeAVYPaJpRYRsaIU+M2NbtOtXc7UKla/H6DP6Y Pie4aL3Df71FkgusCmsPxFSTGSGRbldJ3GoN6ptINsXBz8jJppWJpWy/NmrTZPdaKG oGmvbt7tiH69KB66Z7DTGd4Mwk3BdjzhCkKOzmt06QHD2RwwF9SGnN0X/zHSKhOn3z uXPtWQBMKQmCtRJwnresjGzL6zodx17e+fz194NKu0MmnK87sCsKuIOfV+oEgX0rSi PDZVkpoqT292UGLU+fiB5CBMYtF8EckfEKrKHtGfyMhefBHOpOtLqFK0OTey6VwGo6 MMADUMKFHyRZw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nD47r-003VcX-L1; Thu, 27 Jan 2022 12:43:43 +0000 Date: Thu, 27 Jan 2022 12:43:43 +0000 Message-ID: <87wnil5oxs.wl-maz@kernel.org> From: Marc Zyngier To: "Russell King (Oracle)" Subject: Re: [PATCH v5 08/69] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set In-Reply-To: References: <20211129200150.351436-1-maz@kernel.org> <20211129200150.351436-9-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com, christoffer.dall@arm.com, jintack@cs.columbia.edu, haibo.xu@linaro.org, gankulkarni@os.amperecomputing.com, james.morse@arm.com, suzuki.poulose@arm.com, alexandru.elisei@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kernel-team@android.com, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , kvmarm@lists.cs.columbia.edu, Ganapatrao Kulkarni , linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 17 Jan 2022 17:06:10 +0000, "Russell King (Oracle)" wrote: > > On Mon, Nov 29, 2021 at 08:00:49PM +0000, Marc Zyngier wrote: > > From: Christoffer Dall > > > > Reset the VCPU with PSTATE.M = EL2h when the nested virtualization > > feature is enabled on the VCPU. > > > > Signed-off-by: Christoffer Dall > > [maz: rework register reset not to use empty data structures] > > Signed-off-by: Marc Zyngier > > Reviewed-by: Russell King (Oracle) > > However, a couple of comments below. > > > --- > > arch/arm64/kvm/reset.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 426bd7fbc3fd..38a7182819fb 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -27,6 +27,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > /* Maximum phys_shift supported for any VM on this host */ > > @@ -38,6 +39,9 @@ static u32 kvm_ipa_limit; > > #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > > PSR_F_BIT | PSR_D_BIT) > > > > +#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > > + PSR_F_BIT | PSR_D_BIT) > > + > > #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > > PSR_AA32_I_BIT | PSR_AA32_F_BIT) > > > > @@ -176,8 +180,8 @@ static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) > > return false; > > > > - /* MTE is incompatible with AArch32 */ > > - if (kvm_has_mte(vcpu->kvm) && is32bit) > > + /* MTE and NV are incompatible with AArch32 */ > > + if ((kvm_has_mte(vcpu->kvm) || nested_virt_in_use(vcpu)) && is32bit) > > return false; > > It seems we have a bunch of: > > if (something && is32bit) > return false; > > tests here - would it make sense to do: > > if (is32bit) { > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) > return false; > > /* MTE is incompatible with AArch32 */ > if (kvm_has_mte(vcpu->kvm)) > return false; > > /* NV is incompatible with AArch32 */ > if (nested_virt_in_use(vcpu)) > return false; > } > > in terms of improved readability? Agreed. I've now reworked to follow this pattern. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm