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Fri, 21 Aug 2020 13:45:40 +0100 MIME-Version: 1.0 Date: Fri, 21 Aug 2020 13:45:40 +0100 From: Marc Zyngier To: Catalin Marinas Subject: Re: [PATCH v4 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 In-Reply-To: <20200821122633.GC6823@gaia> References: <20200803193127.3012242-1-robh@kernel.org> <20200803193127.3012242-4-robh@kernel.org> <20200821120659.GB6823@gaia> <20200821121209.GB20833@willie-the-truck> <20200821122633.GC6823@gaia> User-Agent: Roundcube Webmail/1.4.7 Message-ID: <8c641833ff20d5a35981c456d4fe1d5a@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, ascull@google.com, julien.thierry.kdev@gmail.com, kvmarm@lists.cs.columbia.edu X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: Rob Herring , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 2020-08-21 13:26, Catalin Marinas wrote: > On Fri, Aug 21, 2020 at 01:12:10PM +0100, Will Deacon wrote: >> On Fri, Aug 21, 2020 at 01:07:00PM +0100, Catalin Marinas wrote: >> > On Mon, Aug 03, 2020 at 01:31:27PM -0600, Rob Herring wrote: >> > > @@ -979,6 +980,14 @@ >> > > write_sysreg(__scs_new, sysreg); \ >> > > } while (0) >> > > >> > > +#define read_sysreg_par() ({ \ >> > > + u64 par; \ >> > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ >> > > + par = read_sysreg(par_el1); \ >> > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ >> > > + par; \ >> > > +}) >> > >> > I was about to queue this up but one more point to clarify: can we get >> > an interrupt at either side of the PAR_EL1 read and the handler do a >> > device read, triggering the erratum? Do we need a DMB at exception >> > entry/return? >> >> Disabling irqs around the PAR access would be simpler, I think >> (assuming >> this is needed). > > This wouldn't work if it interrupts a guest. If we take an interrupt either side of the PAR_EL1 read and that we fully exit, the saving of PAR_EL1 on the way out solves the problem. If we don't fully exit, but instead reenter the guest immediately (fixup_guest_exit() returns true), we'd need a DMB at that point, at least because of the GICv2 proxying code which performs device accesses on the guest's behalf. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm