From: Eric Auger <eric.auger@redhat.com>
To: Khushit Shah <khushit.shah@nutanix.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"cohuck@redhat.com" <cohuck@redhat.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
"maz@kernel.org" <maz@kernel.org>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
"berrange@redhat.com" <berrange@redhat.com>,
"abologna@redhat.com" <abologna@redhat.com>,
"jdenemar@redhat.com" <jdenemar@redhat.com>,
"gshan@redhat.com" <gshan@redhat.com>,
"skolothumtho@nvidia.com" <skolothumtho@nvidia.com>,
"sebott@redhat.com" <sebott@redhat.com>,
"armbru@redhat.com" <armbru@redhat.com>,
"philmd@linaro.org" <philmd@linaro.org>,
"yangjinqian1@huawei.com" <yangjinqian1@huawei.com>,
Shaju Abraham <shaju.abraham@nutanix.com>,
Mark Cave-Ayland <mark.caveayland@nutanix.com>,
Prerna Saxena <prerna.saxena@nutanix.com>
Subject: Re: [RFC PATCH v3 02/19] scripts: bug fixes in update-aarch64-cpu-sysreg-properties
Date: Fri, 14 Aug 2026 15:45:08 +0200 [thread overview]
Message-ID: <8d9e5cef-526e-4d4f-86a2-d86bdaeabd34@redhat.com> (raw)
In-Reply-To: <7B85F7CA-C4CB-4EAD-BCB1-6D2135934F5B@nutanix.com>
On 8/3/26 4:32 PM, Khushit Shah wrote:
>
>> On 20 Jul 2026, at 7:54 PM, Eric Auger <eric.auger@redhat.com> wrote:
>>
>> !-------------------------------------------------------------------|
>> CAUTION: External Email
>>
>> |-------------------------------------------------------------------!
>>
>>
>>
>> On 7/16/26 11:38 PM, Khushit Shah wrote:
>>> - handle quoted bitstrings and decimal
>>> - skip Values.ValueRange entries.
>> The above is the issue you reported on my v6. See my comment on the
>> other thread.
> Acked.
>>> - Emit unique RESx_{lsb} names for reserved fields so no two fields in
>>> a register share a name.
>> The requirement for naming RES field needs to be explained. I understand
>> that now you expose all fields including those which are not writable it
>> may be required but at this stage I still fail why this is requested.
> I think we don’t need to expose RES fields to users.
> I was thinking of case where a RES0 field is repurposed for
> something else, but that should be taken care by zeroing the
> ID regs array before initiating the named model hierarchy.
> (RES1 field in CTR_EL0 needs some handling).
I also think so. you can rely on AARCHMRS desc to identify the right
default values.
>
> On why we even need to expose non-writable fields:
> - Assume some non-writable field mismatches for the model and
> host, why do we want to stop users from explicitly overriding
> the model's field value to host value?
I agree this needs to be checked. However as I suggested I think you can
avoid exposing them to the end-users as props. You just need to read the
value from host and compare it with the value set in the named model.
>
>>> - Emit a dummy 64-bit VAL field for registers with no defined fields,
>>> such as AIDR_EL1 and REVIDR_EL1.
>> This is yet another functional change that could be separate.
> Acked, will do in v4.
Thanks
Eric
>
>> Thanks
>>
>> Eric
>>> Signed-off-by: Khushit Shah <khushit.shah@nutanix.com>
>>> ---
>>> .../update-aarch64-cpu-sysreg-properties.py | 67 +++++++++++++------
>>> 1 file changed, 45 insertions(+), 22 deletions(-)
>>> mode change 100644 => 100755 scripts/update-aarch64-cpu-sysreg-properties.py
>>>
>>> diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/update-aarch64-cpu-sysreg-properties.py
>>> old mode 100644
>>> new mode 100755
>>> index 9e829fda2e..ecc35db528
>>> --- a/scripts/update-aarch64-cpu-sysreg-properties.py
>>> +++ b/scripts/update-aarch64-cpu-sysreg-properties.py
>>> @@ -106,6 +106,29 @@ def collect_fields(item, bit_offset=0):
>>>
>>> return fields
>>>
>>> +def parse_value_int(raw_val):
>>> + if raw_val is None or isinstance(raw_val, bool):
>>> + return None
>>> +
>>> + # may already be real number
>>> + if isinstance(raw_val, int):
>>> + return raw_val
>>> +
>>> + raw_str = str(raw_val).strip()
>>> +
>>> + if "'" in raw_str:
>>> + # quoted bitstring like "'0100'"
>>> + bits = raw_str.replace("'", "")
>>> + try:
>>> + return int(bits, 2)
>>> + except ValueError:
>>> + return None
>>> +
>>> + # unquoted, try decimal
>>> + try:
>>> + return int(raw_str, 0)
>>> + except ValueError:
>>> + return None
>>>
>>> def extract_field_enums(field):
>>> enums = []
>>> @@ -124,32 +147,23 @@ def extract_field_enums(field):
>>> if not isinstance(val_entries, list):
>>> return enums
>>>
>>> + # A Values.ValueRange field specifies start and end value for a range.
>>> + # Don't enumerate anything for them.
>>> + for val_entry in val_entries:
>>> + if isinstance(val_entry, dict) and \
>>> + val_entry.get("_type") == "Values.ValueRange":
>>> + return []
>>> +
>>> for val_entry in val_entries:
>>> if not isinstance(val_entry, dict):
>>> continue
>>> -
>>> +
>>> if val_entry.get("_type") == "Values.Value":
>>> - raw_val = val_entry.get("value")
>>> - if raw_val is None:
>>> + int_val = parse_value_int(val_entry.get("value"))
>>> + if int_val is None:
>>> continue
>>> -
>>> - # some of the values have ' like "'0100'"
>>> - raw_val_str = str(raw_val).strip().replace("'", "")
>>> -
>>> - try:
>>> - # convert into bin
>>> - int_val = int(raw_val_str, 2)
>>> - except ValueError:
>>> - try:
>>> - # Fallback to dec if not bin
>>> - int_val = int(raw_val_str, 0)
>>> - except ValueError:
>>> - continue
>>> -
>>> - enums.append({
>>> - 'value': int_val
>>> - })
>>> -
>>> + enums.append({'value': int_val})
>>> +
>>> return enums
>>>
>>> def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_path):
>>> @@ -210,7 +224,7 @@ def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_path):
>>> msb > current_fieldset_fields[unique_key]['msb']:
>>> enums = extract_field_enums(val)
>>> current_fieldset_fields[unique_key] = {
>>> - 'raw_name': name,
>>> + 'raw_name': unique_key,
>>> 'lsb': lsb,
>>> 'msb': msb,
>>> 'width': width,
>>> @@ -238,6 +252,15 @@ def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_path):
>>> # Sort decreasing lsbs
>>> sorted_fields = sorted(unique_fields.items(),
>>> key=lambda x: x[1]['lsb'], reverse=True)
>>> + if len(sorted_fields) == 0:
>>> + # cases like REVIDR_EL1 and AIDR_EL1.
>>> + # augment a dummy fields VAL.
>>> + sorted_fields.append(('VAL', {
>>> + 'lsb': 0,
>>> + 'msb': 63,
>>> + 'width': 64,
>>> + 'enums': []
>>> + }))
>>>
>>> for unique_key, bits in sorted_fields:
>>> enums_list = bits.get('enums', [])
next prev parent reply other threads:[~2026-08-14 13:45 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-16 21:38 [RFC PATCH v3 00/19] named CPU models for Arm64 on KVM Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 01/19] target/arm/sysreg: regenerate cpu-sysregs.h.inc Khushit Shah
2026-07-20 12:11 ` Eric Auger
2026-08-03 14:22 ` Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 02/19] scripts: bug fixes in update-aarch64-cpu-sysreg-properties Khushit Shah
2026-07-20 14:24 ` Eric Auger
2026-08-03 14:32 ` Khushit Shah
2026-08-14 13:45 ` Eric Auger [this message]
2026-07-16 21:38 ` [RFC PATCH v3 03/19] target/arm: regenerate cpu-idregs.h.inc Khushit Shah
2026-07-20 14:39 ` Eric Auger
2026-08-03 14:34 ` Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 04/19] target/arm: expose all ID regs fields as properties Khushit Shah
2026-07-21 14:44 ` Eric Auger
2026-08-03 15:05 ` Khushit Shah
2026-08-14 13:54 ` Eric Auger
2026-07-16 21:38 ` [RFC PATCH v3 05/19] target/arm/kvm: enable writable implementation ID registers Khushit Shah
2026-07-21 15:03 ` Eric Auger
2026-08-03 15:46 ` Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 06/19] target/arm/kvm: Read all ID registers from KVM Khushit Shah
2026-07-22 6:54 ` Eric Auger
2026-08-03 15:47 ` Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 07/19] target/arm/kvm: handle special ID registers cases when reading " Khushit Shah
2026-07-22 12:32 ` Eric Auger
2026-08-03 15:52 ` Khushit Shah
2026-08-14 13:55 ` Eric Auger
2026-07-16 21:38 ` [RFC PATCH v3 08/19] target/arm/kvm: Handle writeback for special ID register fields Khushit Shah
2026-07-22 12:05 ` Eric Auger
2026-07-26 13:56 ` Eric Auger
2026-08-03 16:03 ` Khushit Shah
2026-08-14 14:04 ` Eric Auger
2026-07-16 21:38 ` [RFC PATCH v3 09/19] target/arm: Add named cpu model infra + graviton3 named model Khushit Shah
2026-07-26 13:14 ` Eric Auger
2026-07-26 13:34 ` Eric Auger
2026-08-05 11:35 ` Khushit Shah
2026-08-14 15:40 ` Eric Auger
2026-07-16 21:38 ` [RFC PATCH v3 10/19] target/arm: Add Nvidia Grace " Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 11/19] target/arm: fix sve and pauth finalize for named cpu models Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 12/19] target/arm: Introduce stub files required for qmp support Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 13/19] target/arm/qmp: add named models and properties to cpu-model-expansion Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 14/19] target/arm/kvm: compute supported values for ID register fields Khushit Shah
2026-07-26 14:22 ` Eric Auger
2026-08-05 9:58 ` Khushit Shah
2026-08-14 15:34 ` Eric Auger
2026-07-16 21:38 ` [RFC PATCH v3 15/19] target/arm/kvm: introduce kvm_arm_get_host_isar helper Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 16/19] qmp: add query-cpu-props-info command Khushit Shah
2026-07-20 13:21 ` Markus Armbruster
2026-08-03 16:05 ` Khushit Shah
2026-08-04 6:05 ` Markus Armbruster
2026-08-04 6:07 ` Khushit Shah
2026-08-04 6:30 ` Khushit Shah
2026-08-04 6:51 ` Markus Armbruster
2026-08-05 6:48 ` Khushit Shah
2026-08-05 6:58 ` Markus Armbruster
2026-08-05 7:32 ` Khushit Shah
2026-08-05 13:22 ` Markus Armbruster
2026-08-06 9:24 ` Khushit Shah
2026-08-04 6:45 ` Markus Armbruster
2026-08-05 6:47 ` Khushit Shah
2026-08-05 6:57 ` Markus Armbruster
2026-08-05 7:32 ` Khushit Shah
2026-08-14 13:38 ` Eric Auger
2026-07-16 21:38 ` [RFC PATCH v3 17/19] target/arm: Report 0 as supported for ID fields gated by vCPU init flags Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 18/19] target/arm/qmp: hook blockers in query-cpu-definitions Khushit Shah
2026-07-16 21:38 ` [RFC PATCH v3 19/19] target/arm/kvm: fix host model writeback when kernel supports EL2 Khushit Shah
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8d9e5cef-526e-4d4f-86a2-d86bdaeabd34@redhat.com \
--to=eric.auger@redhat.com \
--cc=abologna@redhat.com \
--cc=armbru@redhat.com \
--cc=berrange@redhat.com \
--cc=cohuck@redhat.com \
--cc=gshan@redhat.com \
--cc=jdenemar@redhat.com \
--cc=khushit.shah@nutanix.com \
--cc=kvmarm@lists.linux.dev \
--cc=mark.caveayland@nutanix.com \
--cc=maz@kernel.org \
--cc=oliver.upton@linux.dev \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=prerna.saxena@nutanix.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sebott@redhat.com \
--cc=shaju.abraham@nutanix.com \
--cc=skolothumtho@nvidia.com \
--cc=yangjinqian1@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox