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[34.83.12.150]) by smtp.gmail.com with ESMTPSA id o10sm536969pfh.67.2021.06.02.16.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 16:26:55 -0700 (PDT) Date: Wed, 2 Jun 2021 16:26:51 -0700 From: Ricardo Koller To: Andrew Jones Subject: Re: [PATCH v3 5/5] KVM: arm64: selftests: get-reg-list: Split base and pmu registers Message-ID: References: <20210531103344.29325-1-drjones@redhat.com> <20210531103344.29325-6-drjones@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210531103344.29325-6-drjones@redhat.com> Cc: kvm@vger.kernel.org, maz@kernel.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, May 31, 2021 at 12:33:44PM +0200, Andrew Jones wrote: > Since KVM commit 11663111cd49 ("KVM: arm64: Hide PMU registers from > userspace when not available") the get-reg-list* tests have been > failing with > > ... > ... There are 74 missing registers. > The following lines are missing registers: > ... > > where the 74 missing registers are all PMU registers. This isn't a > bug in KVM that the selftest found, even though it's true that a > KVM userspace that wasn't setting the KVM_ARM_VCPU_PMU_V3 VCPU > flag, but still expecting the PMU registers to be in the reg-list, > would suddenly no longer have their expectations met. In that case, > the expectations were wrong, though, so that KVM userspace needs to > be fixed, and so does this selftest. The fix for this selftest is to > pull the PMU registers out of the base register sublist into their > own sublist and then create new, pmu-enabled vcpu configs which can > be tested. > > Signed-off-by: Andrew Jones Reviewed-by: Ricardo Koller > --- > .../selftests/kvm/aarch64/get-reg-list.c | 39 +++++++++++++++---- > 1 file changed, 31 insertions(+), 8 deletions(-) > > diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c > index b46b8a1fdc0c..a16c8f05366c 100644 > --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c > +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c > @@ -637,7 +637,7 @@ int main(int ac, char **av) > * The current blessed list was primed with the output of kernel version > * v4.15 with --core-reg-fixup and then later updated with new registers. > * > - * The blessed list is up to date with kernel version v5.10-rc5 > + * The blessed list is up to date with kernel version v5.13-rc3 > */ > static __u64 base_regs[] = { > KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[0]), > @@ -829,8 +829,6 @@ static __u64 base_regs[] = { > ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ > ARM64_SYS_REG(3, 0, 6, 0, 0), /* FAR_EL1 */ > ARM64_SYS_REG(3, 0, 7, 4, 0), /* PAR_EL1 */ > - ARM64_SYS_REG(3, 0, 9, 14, 1), /* PMINTENSET_EL1 */ > - ARM64_SYS_REG(3, 0, 9, 14, 2), /* PMINTENCLR_EL1 */ > ARM64_SYS_REG(3, 0, 10, 2, 0), /* MAIR_EL1 */ > ARM64_SYS_REG(3, 0, 10, 3, 0), /* AMAIR_EL1 */ > ARM64_SYS_REG(3, 0, 12, 0, 0), /* VBAR_EL1 */ > @@ -839,6 +837,16 @@ static __u64 base_regs[] = { > ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ > ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ > ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ > + ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ > + ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ > + ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ > + ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ > + ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ > +}; > + > +static __u64 pmu_regs[] = { > + ARM64_SYS_REG(3, 0, 9, 14, 1), /* PMINTENSET_EL1 */ > + ARM64_SYS_REG(3, 0, 9, 14, 2), /* PMINTENCLR_EL1 */ > ARM64_SYS_REG(3, 3, 9, 12, 0), /* PMCR_EL0 */ > ARM64_SYS_REG(3, 3, 9, 12, 1), /* PMCNTENSET_EL0 */ > ARM64_SYS_REG(3, 3, 9, 12, 2), /* PMCNTENCLR_EL0 */ > @@ -848,8 +856,6 @@ static __u64 base_regs[] = { > ARM64_SYS_REG(3, 3, 9, 13, 0), /* PMCCNTR_EL0 */ > ARM64_SYS_REG(3, 3, 9, 14, 0), /* PMUSERENR_EL0 */ > ARM64_SYS_REG(3, 3, 9, 14, 3), /* PMOVSSET_EL0 */ > - ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ > - ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ > ARM64_SYS_REG(3, 3, 14, 8, 0), > ARM64_SYS_REG(3, 3, 14, 8, 1), > ARM64_SYS_REG(3, 3, 14, 8, 2), > @@ -913,9 +919,6 @@ static __u64 base_regs[] = { > ARM64_SYS_REG(3, 3, 14, 15, 5), > ARM64_SYS_REG(3, 3, 14, 15, 6), > ARM64_SYS_REG(3, 3, 14, 15, 7), /* PMCCFILTR_EL0 */ > - ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ > - ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ > - ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ > }; > > static __u64 vregs[] = { > @@ -1015,6 +1018,8 @@ static __u64 sve_rejects_set[] = { > { "base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), } > #define VREGS_SUBLIST \ > { "vregs", .regs = vregs, .regs_n = ARRAY_SIZE(vregs), } > +#define PMU_SUBLIST \ > + { "pmu", .regs = pmu_regs, .regs_n = ARRAY_SIZE(pmu_regs), } > #define SVE_SUBLIST \ > { "sve", .capability = KVM_CAP_ARM_SVE, .feature = KVM_ARM_VCPU_SVE, .finalize = true, \ > .regs = sve_regs, .regs_n = ARRAY_SIZE(sve_regs), \ > @@ -1027,6 +1032,14 @@ static struct vcpu_config vregs_config = { > {0}, > }, > }; > +static struct vcpu_config vregs_pmu_config = { > + .sublists = { > + BASE_SUBLIST, > + VREGS_SUBLIST, > + PMU_SUBLIST, > + {0}, > + }, > +}; > static struct vcpu_config sve_config = { > .sublists = { > BASE_SUBLIST, > @@ -1034,9 +1047,19 @@ static struct vcpu_config sve_config = { > {0}, > }, > }; > +static struct vcpu_config sve_pmu_config = { > + .sublists = { > + BASE_SUBLIST, > + SVE_SUBLIST, > + PMU_SUBLIST, > + {0}, > + }, > +}; > > static struct vcpu_config *vcpu_configs[] = { > &vregs_config, > + &vregs_pmu_config, > &sve_config, > + &sve_pmu_config, > }; > static int vcpu_configs_n = ARRAY_SIZE(vcpu_configs); > -- > 2.31.1 > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm