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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id u12sm1042822iop.52.2021.11.04.09.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Nov 2021 09:14:36 -0700 (PDT) Date: Thu, 4 Nov 2021 16:14:33 +0000 From: Oliver Upton To: Reiji Watanabe Subject: Re: [RFC PATCH v2 02/28] KVM: arm64: Save ID registers' sanitized value per vCPU Message-ID: References: <20211103062520.1445832-1-reijiw@google.com> <20211103062520.1445832-3-reijiw@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211103062520.1445832-3-reijiw@google.com> Cc: kvm@vger.kernel.org, Marc Zyngier , Peter Shier , Will Deacon , Paolo Bonzini , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Reiji, On Tue, Nov 02, 2021 at 11:24:54PM -0700, Reiji Watanabe wrote: > Extend sys_regs[] of kvm_cpu_context for ID registers and save ID > registers' sanitized value in the array for the vCPU at the first > vCPU reset. Use the saved ones when ID registers are read by > userspace (via KVM_GET_ONE_REG) or the guest. Based on my understanding of the series, it appears that we require the CPU identity to be the same amongst all vCPUs in a VM. Is there any value in keeping a single copy in kvm_arch? > Signed-off-by: Reiji Watanabe > --- > arch/arm64/include/asm/kvm_host.h | 10 ++++++++++ > arch/arm64/kvm/sys_regs.c | 24 ++++++++++++++++-------- > 2 files changed, 26 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 9b5e7a3b6011..0cd351099adf 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -145,6 +145,14 @@ struct kvm_vcpu_fault_info { > u64 disr_el1; /* Deferred [SError] Status Register */ > }; > > +/* > + * (Op0, Op1, CRn, CRm, Op2) of ID registers is (3, 0, 0, crm, op2), > + * where 0<=crm<8, 0<=op2<8. > + */ > +#define KVM_ARM_ID_REG_MAX_NUM 64 > +#define IDREG_IDX(id) ((sys_reg_CRm(id) << 3) | sys_reg_Op2(id)) > +#define IDREG_SYS_IDX(id) (ID_REG_BASE + IDREG_IDX(id)) > + > enum vcpu_sysreg { > __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ > MPIDR_EL1, /* MultiProcessor Affinity Register */ > @@ -209,6 +217,8 @@ enum vcpu_sysreg { > CNTP_CVAL_EL0, > CNTP_CTL_EL0, > > + ID_REG_BASE, > + ID_REG_END = ID_REG_BASE + KVM_ARM_ID_REG_MAX_NUM - 1, > /* Memory Tagging Extension registers */ > RGSR_EL1, /* Random Allocation Tag Seed Register */ > GCR_EL1, /* Tag Control Register */ > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 1d46e185f31e..2443440720b4 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -273,7 +273,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, > struct sys_reg_params *p, > const struct sys_reg_desc *r) > { > - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); > + u64 val = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(SYS_ID_AA64MMFR1_EL1)); > u32 sr = reg_to_encoding(r); > > if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { > @@ -1059,12 +1059,11 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu, > return true; > } > > -/* Read a sanitised cpufeature ID register by sys_reg_desc */ > static u64 read_id_reg(const struct kvm_vcpu *vcpu, > struct sys_reg_desc const *r, bool raz) > { > u32 id = reg_to_encoding(r); > - u64 val = raz ? 0 : read_sanitised_ftr_reg(id); > + u64 val = raz ? 0 : __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)); > > switch (id) { > case SYS_ID_AA64PFR0_EL1: > @@ -1174,6 +1173,16 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, > return REG_HIDDEN; > } > > +static void reset_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) > +{ > + u32 id = reg_to_encoding(rd); > + > + if (vcpu_has_reset_once(vcpu)) > + return; > + > + __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)) = read_sanitised_ftr_reg(id); > +} > + > static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > const struct sys_reg_desc *rd, > const struct kvm_one_reg *reg, void __user *uaddr) > @@ -1219,9 +1228,7 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > /* > * cpufeature ID register user accessors > * > - * For now, these registers are immutable for userspace, so no values > - * are stored, and for set_id_reg() we don't allow the effective value > - * to be changed. > + * We don't allow the effective value to be changed. > */ > static int __get_id_reg(const struct kvm_vcpu *vcpu, > const struct sys_reg_desc *rd, void __user *uaddr, > @@ -1375,6 +1382,7 @@ static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, > #define ID_SANITISED(name) { \ > SYS_DESC(SYS_##name), \ > .access = access_id_reg, \ > + .reset = reset_id_reg, \ > .get_user = get_id_reg, \ > .set_user = set_id_reg, \ > .visibility = id_visibility, \ > @@ -1830,8 +1838,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, > if (p->is_write) { > return ignore_write(vcpu, p); > } else { > - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); > - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); > + u64 dfr = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(SYS_ID_AA64DFR0_EL1)); > + u64 pfr = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(SYS_ID_AA64PFR0_EL1)); > u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); > > p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | > -- > 2.33.1.1089.g2158813163f-goog > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm