From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2973D6FDC for ; Fri, 17 Mar 2023 16:02:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6C151C433EF; Fri, 17 Mar 2023 16:02:09 +0000 (UTC) Date: Fri, 17 Mar 2023 16:02:06 +0000 From: Catalin Marinas To: Kristina Martsenko Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Mark Brown , Luis Machado , Vladimir Murzin , linux-kernel@vger.kernel.org Subject: Re: [PATCH 08/10] arm64: mops: handle single stepping after MOPS exception Message-ID: References: <20230216160012.272345-1-kristina.martsenko@arm.com> <20230216160012.272345-9-kristina.martsenko@arm.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230216160012.272345-9-kristina.martsenko@arm.com> On Thu, Feb 16, 2023 at 04:00:10PM +0000, Kristina Martsenko wrote: > When a MOPS main or epilogue instruction is being executed, the task may > get scheduled on a different CPU and restart execution from the prologue > instruction. If the main or epilogue instruction is being single stepped > then it makes sense to finish the step and take the step exception > before starting to execute the next (prologue) instruction. So > fast-forward the single step state machine when taking a MOPS exception. > > This means that if a main or epilogue instruction is single stepped with > ptrace, the debugger will sometimes observe the PC moving back to the > prologue instruction. (As already mentioned, this should be rare as it > only happens when the task is scheduled to another CPU during the step.) > > This also ensures that perf breakpoints count prologue instructions > consistently (i.e. every time they are executed), rather than skipping > them when there also happens to be a breakpoint on a main or epilogue > instruction. > > Signed-off-by: Kristina Martsenko Acked-by: Catalin Marinas