From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-34.mta0.migadu.com (out-34.mta0.migadu.com [91.218.175.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A686E1548A for ; Wed, 14 Jun 2023 23:06:46 +0000 (UTC) Date: Wed, 14 Jun 2023 23:06:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1686784004; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=PD1AUBQIxRJCrdxHVZaId+vzfuWrvKkMXGc2KFnMudM=; b=pjwN+kdJW+l9Eogn7Pw/kv3xVQ0IAt6DE5Wqkwb5jsBFEh+u7+1V5oMSZEHuoeN+g+Fa2e 7xSxxA+2E3VDMIYkDbK2IW1CQ/PqXYQlrNcOzI3rymT89g3V+rHjteqP9kDsdl8txP73NK 68hS8e1H68YzBIoZcMsmIWvo23N8iOs= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Catalin Marinas Cc: kvmarm@lists.linux.dev, Marc Zyngier , James Morse , Suzuki K Poulose , Zenghui Yu , Will Deacon , linux-arm-kernel@lists.infradead.org, Darren Hart , D Scott Phillips Subject: Re: [PATCH 0/3] KVM: arm64: Work around Ampere1 erratum AC03_CPU_38 Message-ID: References: <20230609220104.1836988-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT Hey Catalin, On Wed, Jun 14, 2023 at 05:57:55PM +0100, Catalin Marinas wrote: > On Fri, Jun 09, 2023 at 10:01:01PM +0000, Oliver Upton wrote: > > Small series to work around a CPU erratum on AmpereOne. While the > > implementation does not advertise support for FEAT_HAFDBS (due to > > another erratum), the associated control bits do not have RES0 behavior > > as required by the architecture. > > > > Usage of HAFDBS at stage-1 is unaffected, since HA and HD are only > > enabled on implementations that advertise the feature. However, KVM > > relies on HA having RES0 semantics if the feature isn't implemented. The > > end result is that KVM enables a broken hardware access flag > > implementation that could lead to correctness issues. > > Just curious, what's the correctness issue here? The access flag is > mostly indicative of which pages are old for swapping out/discarding. > It's not like the dirty state which would be dangerous if we get wrong. I probably could have helped out by giving the full context. The software-observable behavior on this system is that the A or D updates could arrive after a PTE has been marked as invalid, which could corrupt software metadata stuffed into the page tables. We do exactly that at stage-2 in KVM for parallel fault handling, where a magic value indicates a PTE is being updated by another thread. -- Thanks, Oliver