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[34.78.232.44]) by smtp.gmail.com with ESMTPSA id b7-20020a5d4b87000000b00314374145e0sm5614126wrt.67.2023.07.04.07.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 07:18:13 -0700 (PDT) Date: Tue, 4 Jul 2023 14:18:09 +0000 From: Mostafa Saleh To: Sudeep Holla Cc: maz@kernel.org, oliver.upton@linux.dev, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, tabba@google.com, qperret@google.com, will@kernel.org, catalin.marinas@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, james.morse@arm.com, bgardon@google.com, gshan@redhat.com Subject: Re: [PATCH v3] KVM: arm64: Use BTI for nvhe Message-ID: References: <20230530150845.2856828-1-smostafa@google.com> <20230704134136.a5znw4jupt5yp5kg@bogus> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230704134136.a5znw4jupt5yp5kg@bogus> Hi Sudeep, On Tue, Jul 04, 2023 at 02:41:36PM +0100, Sudeep Holla wrote: > On Tue, May 30, 2023 at 03:08:45PM +0000, Mostafa Saleh wrote: > > CONFIG_ARM64_BTI_KERNEL compiles the kernel to support ARMv8.5-BTI. > > However, the nvhe code doesn't make use of it as it doesn't map any > > pages with Guarded Page(GP) bit. > > > > kvm pgtable code is modified to map executable pages with GP bit > > if BTI is enabled for the kernel. > > > > At hyp init, SCTLR_EL2.BT is set to 1 to match EL1 configuration > > (SCTLR_EL1.BT1) set in bti_enable(). > > > > One difference between kernel and nvhe code, is that the kernel maps > > .text with GP while nvhe maps all the executable pages, this makes > > nvhe code need to deal with special initialization code coming from > > other executable sections (.idmap.text). > > For this we need to add bti instruction at the beginning of > > __kvm_handle_stub_hvc as it can be called by __host_hvc through > > branch instruction(br) and unlike SYM_FUNC_START, SYM_CODE_START > > doesn’t add bti instruction at the beginning, and it can’t be modified > > to add it as it is used with vector tables. > > Another solution which is more intrusive is to convert > > __kvm_handle_stub_hvc to a function and inject “bti jc” instead of > > “bti c” in SYM_FUNC_START > > > > I was chasing a bug in linux-next yesterday with protected nVHE(pKVM) and > cpuidle enabled. The system fails to boot. I just bisected the issue to this > patch and also saw this patch landed in the linus tree yesterday/today. One of the challenges of BTI is that we need to add explicit BTI instructions for assembly code. I checked the code to make sure that nothing was missing, but maybe this is not the case. Can you please share more about the issue (is ESR a Branch Target Exception, call stack...) if possible. Also, is this with CONFIG_ARM_PSCI_CPUIDLE? > Not sure if this is something to do with the fact that pKVM skips to > __kvm_handle_stub_hvc in __host_hvc. __kvm_handle_stub_hvc is called from __host_hvc with "br x5" That's why "bti j" was added at the beginning of __kvm_handle_stub_hvc, so this should be fine. > Let me know if you want be to try something. > > -- > Regards, > Sudeep Thanks, Mostafa