From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-224.mta0.migadu.com (out-224.mta0.migadu.com [91.218.175.224]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 224DF1B279 for ; Fri, 15 Sep 2023 20:53:18 +0000 (UTC) Date: Fri, 15 Sep 2023 20:53:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1694811196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=y7OM5v7blYOAJxEJ3s0YCjQVgdsW57nwTu7RUWwmajk=; b=WUgTdPy3r/vauuaDrIYbzKUJBVRiZtdsHsT0S+gxTtgpjItrfnOfVIa5iN5njKOUsxCFwG 3vNVLS+vQx0k1l5eeblNMvEa/3HbVWyRVFq6CPHpqiNYwL+jSnl+uGk9EMrCRNIhTrsGJ5 BuFjAwp4Qecsddpz7fxnU4li3QgtiAk= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Raghavendra Rao Ananta Cc: Marc Zyngier , Alexandru Elisei , James Morse , Suzuki K Poulose , Paolo Bonzini , Zenghui Yu , Shaoqin Huang , Jing Zhang , Reiji Watanabe , Colton Lewis , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v5 08/12] KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest Message-ID: References: <20230817003029.3073210-1-rananta@google.com> <20230817003029.3073210-9-rananta@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230817003029.3073210-9-rananta@google.com> X-Migadu-Flow: FLOW_OUT Hi Raghu, On Thu, Aug 17, 2023 at 12:30:25AM +0000, Raghavendra Rao Ananta wrote: > From: Reiji Watanabe > > KVM does not yet support userspace modifying PMCR_EL0.N (With > the previous patch, KVM ignores what is written by upserspace). typo: userspace > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index ce7de6bbdc967..39ad56a71ad20 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -896,6 +896,7 @@ int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) > * while the latter does not. > */ > kvm->arch.pmcr_n = arm_pmu->num_events - 1; > + kvm->arch.pmcr_n_limit = arm_pmu->num_events - 1; Can't we just get at this through the arm_pmu instance rather than copying it into kvm_arch? > return 0; > } > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 2075901356c5b..c01d62afa7db4 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1086,6 +1086,51 @@ static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, > return 0; > } > > +static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, > + u64 val) > +{ > + struct kvm *kvm = vcpu->kvm; > + u64 new_n, mutable_mask; > + int ret = 0; > + > + new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); > + > + mutex_lock(&kvm->arch.config_lock); > + if (unlikely(new_n != kvm->arch.pmcr_n)) { > + /* > + * The vCPU can't have more counters than the PMU > + * hardware implements. > + */ > + if (new_n <= kvm->arch.pmcr_n_limit) > + kvm->arch.pmcr_n = new_n; > + else > + ret = -EINVAL; > + } Hmm, I'm not so sure about returning an error here. ABI has it that userspace can write any value to PMCR_EL0 successfully. Can we just ignore writes that attempt to set PMCR_EL0.N to something higher than supported by hardware? Our general stance should be that system register fields responsible for feature identification are immutable after the VM has started. -- Thanks, Oliver