From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-196.mta1.migadu.com (out-196.mta1.migadu.com [95.215.58.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 072471FDF for ; Tue, 24 Oct 2023 08:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="oFd6EYkL" Date: Tue, 24 Oct 2023 08:59:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1698137975; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=D6TYYpqy8N97kO8tVC2Cc3XTS86qRouwgud2Yw4OPK4=; b=oFd6EYkL7idjhlxEaG6UTiY53c5RjtDdeG3QcRHlcOHPEzg95lcPHSAzMzHXNHO0bq+jwH S0AjNrrfYFkVGFRIKIhvXqcpVLF/ujPhdmZwVQbJY99KGSuW/VvDTLLF9tS9aslIs6AP4R wBfV8EFFpLCr8xGx0f3ThQAbDEldEms= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Raghavendra Rao Ananta Cc: Marc Zyngier , Alexandru Elisei , James Morse , Suzuki K Poulose , Paolo Bonzini , Zenghui Yu , Shaoqin Huang , Jing Zhang , Reiji Watanabe , Colton Lewis , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v8 05/13] KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} Message-ID: References: <20231020214053.2144305-1-rananta@google.com> <20231020214053.2144305-6-rananta@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231020214053.2144305-6-rananta@google.com> X-Migadu-Flow: FLOW_OUT On Fri, Oct 20, 2023 at 09:40:45PM +0000, Raghavendra Rao Ananta wrote: > For unimplemented counters, the bits in PM{C,I}NTEN{SET,CLR} and > PMOVS{SET,CLR} registers are expected to RAZ. To honor this, > explicitly implement the {get,set}_user functions for these > registers to mask out unimplemented counters for userspace reads > and writes. > > Signed-off-by: Raghavendra Rao Ananta > --- > arch/arm64/kvm/sys_regs.c | 91 ++++++++++++++++++++++++++++++++++++--- > 1 file changed, 85 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index faf97878dfbbb..2e5d497596ef8 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -987,6 +987,45 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu, > + u64 reg, u64 val, bool set) > +{ > + struct kvm *kvm = vcpu->kvm; > + > + mutex_lock(&kvm->arch.config_lock); > + > + /* Make the register immutable once the VM has started running */ This is a considerable change from the existing behavior and lacks justification. These registers, or rather the state that these aliases update, is mutable from the guest. I see no reason for excluding userspace from this behavior. > + if (kvm_vm_has_ran_once(kvm)) { > + mutex_unlock(&kvm->arch.config_lock); > + return; > + } > + > + val &= kvm_pmu_valid_counter_mask(vcpu); > + mutex_unlock(&kvm->arch.config_lock); I'm not entirely sold on taking the config_lock here. - If userspace is doing these ioctls in parallel then it cannot guarantee ordering in the first place, even w/ locking under the hood. Any garbage values will be discarded by KVM_REQ_RELOAD_PMU. - If the VM has already started PMCR.N is immutable, so there is no race. -- Thanks, Oliver