From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3D0F71B5EA8 for ; Tue, 22 Oct 2024 15:56:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729612570; cv=none; b=NtpmHOuhUMQKxL8kB/0YnSxWJarySd43d/gGZgqkdzsLR7esm+Nbl9Xfuwb9LD707GTMt8GlOkiueQNQHhCAiNu4WJHSUbM/7BSh59LuhXmgNPAaIlBbJ+t8TGldpzCDcon/EQ99P47a0nAAG7/5pr8Uj7uh2qgNzzMTcAfewmU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729612570; c=relaxed/simple; bh=GsxhDVnSwwbJhz9Z4aWQKeAoNkCIeYe/rBrBW158ieA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bxsxKWy//bgLk0hHEZz6MoeQSC7eyoc3+qePUXypE3Pm20Xn7a9rpNgJ2VbzRnu96TnPLGzc5LRkGhxS+FmBSj3esZDgewB+sk1EiAUouaWUVkITBL1ObatWbnR0tR/2iHzUpoC3H9F+yKPpVdlEXlNn/tDjHBSXd01wLd93EBs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A24E497; Tue, 22 Oct 2024 08:56:37 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3AB353F73B; Tue, 22 Oct 2024 08:56:05 -0700 (PDT) Date: Tue, 22 Oct 2024 16:56:02 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev Subject: Re: [PATCH 1/3] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Message-ID: References: <20241001043602.1116991-1-anshuman.khandual@arm.com> <20241001043602.1116991-2-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241001043602.1116991-2-anshuman.khandual@arm.com> On Tue, Oct 01, 2024 at 10:06:00AM +0530, Anshuman Khandual wrote: > This adds required field details for ID_AA64DFR1_EL1, and also drops dummy > ftr_raz[] array which is now redundant. These register fields will be used > to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 > later. > > Cc: Catalin Marinas > Cc: Will Deacon > cc: Mark Brown > Cc: Mark Rutland > Cc: Marc Zyngier > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 718728a85430..bd4d85f5dd92 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -530,6 +530,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { > ARM64_FTR_END, > }; > > +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABL_CMPs_SHIFT, 8, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DPFZS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EBEP_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ITE_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABLE_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_PMICNTR_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SPMU_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_CTX_CMPs_SHIFT, 8, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_WRPs_SHIFT, 8, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_BRPs_SHIFT, 8, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SYSPMUID_SHIFT, 8, 0), > + ARM64_FTR_END, > +}; > + Is there some general principle that has been applied here? e.g. is this STRICT unless we know of variation in practice? e.g. it seems a bit odd that ABLE cannot vary while the number of breakpoints can... I suspect we will see systems with mismatched EBEP too, but maybe I'm wrong. Mark. > static const struct arm64_ftr_bits ftr_mvfr0[] = { > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), > @@ -708,10 +723,6 @@ static const struct arm64_ftr_bits ftr_single32[] = { > ARM64_FTR_END, > }; > > -static const struct arm64_ftr_bits ftr_raz[] = { > - ARM64_FTR_END, > -}; > - > #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ > .sys_id = id, \ > .reg = &(struct arm64_ftr_reg){ \ > @@ -784,7 +795,7 @@ static const struct __ftr_reg_entry { > > /* Op1 = 0, CRn = 0, CRm = 5 */ > ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), > - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), > + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1), > > /* Op1 = 0, CRn = 0, CRm = 6 */ > ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), > -- > 2.25.1 >