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[34.140.115.198]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b6425eeb4sm32171989f8f.0.2026.03.24.03.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 03:14:43 -0700 (PDT) Date: Tue, 24 Mar 2026 10:14:40 +0000 From: Vincent Donnefort To: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Marc Zyngier , Oliver Upton , Lorenzo Pieralisi , Sudeep Holla , James Morse , Mark Rutland , Mark Brown , kvmarm@lists.linux.dev Subject: Re: [PATCH v3 5/5] KVM: arm64: Add SMC hook for SME dvmsync erratum Message-ID: References: <20260323162408.4163113-1-catalin.marinas@arm.com> <20260323162408.4163113-6-catalin.marinas@arm.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260323162408.4163113-6-catalin.marinas@arm.com> On Mon, Mar 23, 2026 at 04:24:05PM +0000, Catalin Marinas wrote: > From: James Morse > > C1-Pro cores with SME have an erratum where TLBI+DSB does not complete > all outstanding SME accesses. Instead a DSB needs to be executed on the > affecteed CPUs. The implication is pages cannot be unmapped from the > host stage2 then provided to the guest. Host SME accesses may occur > after this point. > > This erratum breaks pKVM's guarantees, and the workaround is hard to > implement as EL2 and EL1 share a security state meaning EL1 can mask > IPI sent by EL2, leading to interrupt blackouts. > > Instead, do this in EL3. This has the advantage of a separate security > state, meaning lower EL cannot mask the IPI. It is also simpler for EL3 > to know about CPUs that are off or in PSCI's CPU_SUSPEND. > > Add the needed hook. > > Signed-off-by: James Morse > Signed-off-by: Catalin Marinas > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: Will Deacon > Cc: Mark Rutland > Cc: Lorenzo Pieralisi > Cc: Sudeep Holla In case this goes in before Will's p-guest series and with just a small comment below: Reviewed-by: Vincent Donnefort > --- > arch/arm64/kvm/hyp/nvhe/mem_protect.c | 17 +++++++++++++++++ > include/linux/arm-smccc.h | 6 ++++++ > 2 files changed, 23 insertions(+) > > diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c > index 38f66a56a766..ef8afbdd421b 100644 > --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c > +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c > @@ -5,6 +5,8 @@ > */ > > #include > +#include > + > #include > #include > #include > @@ -28,6 +30,15 @@ static struct hyp_pool host_s2_pool; > static DEFINE_PER_CPU(struct pkvm_hyp_vm *, __current_vm); > #define current_vm (*this_cpu_ptr(&__current_vm)) > > +static void pkvm_sme_dvmsync_fw_call(void) > +{ > + if (alternative_has_cap_unlikely(ARM64_WORKAROUND_4193714)) { > + struct arm_smccc_res res; > + > + arm_smccc_1_1_smc(ARM_SMCCC_CPU_WORKAROUND_4193714, &res); With hyp tracing in kvmarm/next, this should be hyp_smccc_1_1_smc(). > + } > +} > + > static void guest_lock_component(struct pkvm_hyp_vm *vm) > { > hyp_spin_lock(&vm->lock); > @@ -553,6 +564,12 @@ int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id) > if (ret) > return ret; > > + /* > + * After stage2 maintenance has happened, but before the page owner has > + * changed. > + */ > + pkvm_sme_dvmsync_fw_call(); > + > /* Don't forget to update the vmemmap tracking for the host */ > if (owner_id == PKVM_ID_HOST) > __host_update_page_state(addr, size, PKVM_PAGE_OWNED); > diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h > index 50b47eba7d01..e7195750d21b 100644 > --- a/include/linux/arm-smccc.h > +++ b/include/linux/arm-smccc.h > @@ -105,6 +105,12 @@ > ARM_SMCCC_SMC_32, \ > 0, 0x3fff) > > +/* C1-Pro erratum 4193714: SME DVMSync early acknowledgement */ > +#define ARM_SMCCC_CPU_WORKAROUND_4193714 \ > + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ > + ARM_SMCCC_SMC_32, \ > + ARM_SMCCC_OWNER_CPU, 0x10) > + > #define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ > ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ > ARM_SMCCC_SMC_32, \ >