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[35.205.13.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b646b0b0csm36743525f8f.15.2026.03.24.08.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 08:05:37 -0700 (PDT) Date: Tue, 24 Mar 2026 15:05:34 +0000 From: Sebastian Ene To: Vincent Donnefort Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, android-kvm@google.com, catalin.marinas@arm.com, joey.gouly@arm.com, mark.rutland@arm.com, maz@kernel.org, oupton@kernel.org, suzuki.poulose@arm.com, tabba@google.com, will@kernel.org, yuzenghui@huawei.com Subject: Re: [PATCH] KVM: arm64: Inject UNDEF when host is executing an smc with imm16 != 0 Message-ID: References: <20260324135728.3532400-1-sebastianene@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Mar 24, 2026 at 02:18:04PM +0000, Vincent Donnefort wrote: > On Tue, Mar 24, 2026 at 02:09:50PM +0000, Vincent Donnefort wrote: > > On Tue, Mar 24, 2026 at 02:06:40PM +0000, Vincent Donnefort wrote: > > > On Tue, Mar 24, 2026 at 01:57:28PM +0000, Sebastian Ene wrote: > > > > The ARM Service Calling Convention (SMCCC) specifies that the function > > > > identifier and parameters should be passed in registers, leaving the > > > > 16-bit immediate field of the SMC instruction un-handled. > > > > Currently, our pKVM handler ignores the immediate value, which could lead > > > > to non-compliant software relying on implementation-defined behavior. > > > > Enforce the host kernel running under pKVM to use an immediate value > > > > of 0 by decoding the ISS from the ESR_EL2 and inject an undefined > > > > instruction exception back to the caller. > > > > > > > > Signed-off-by: Sebastian Ene > > > > --- > > > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 7 ++++++- > > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > > > > index e7790097db93..ff6a90a4a4c7 100644 > > > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c > > > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > > > > @@ -756,13 +756,18 @@ static bool handle_host_mte(u64 esr) > > > > void handle_trap(struct kvm_cpu_context *host_ctxt) > > > > { > > > > u64 esr = read_sysreg_el2(SYS_ESR); > > > > + u16 imm16; > > > > > > > > switch (ESR_ELx_EC(esr)) { > > > > case ESR_ELx_EC_HVC64: > > > > handle_host_hcall(host_ctxt); > > > > break; > > > > case ESR_ELx_EC_SMC64: > > > > - handle_host_smc(host_ctxt); > > > > + imm16 = esr & U16_MAX; > > > > + if (!imm16) > > > > > > if (ESR_ELx_xVC_IMM_MASK(esr)) ? > > > > > > Also, I can't find void inject_undef64(void); I think you need a vcpu for that? > > > > Ah my bad, handle_host_mte() introduced it! > > > > > > > > > + handle_host_smc(host_ctxt); > > > > + else > > > > + inject_undef64(); > > Could it be better to return SMCCC_RET_NOT_SUPPORTED? Right, I will do that since it seems this is the correct approach. > > > > > break; > > > > case ESR_ELx_EC_IABT_LOW: > > > > case ESR_ELx_EC_DABT_LOW: > > > > -- > > > > 2.53.0.983.g0bb29b3bc5-goog > > > > Thanks, Sebastian