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Mon, 7 Sep 2026 21:24:53 +0000 (UTC) Received: from sm-arm-grace07 (unknown [10.124.178.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2uksmom1.o.css.fujitsu.com (Postfix) with ESMTPS id 641E81800170; Mon, 7 Sep 2026 21:24:48 +0000 (UTC) Date: Tue, 8 Sep 2026 06:24:45 +0900 From: Itaru Kitayama To: Fuad Tabba Cc: Marc Zyngier , Oliver Upton , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Takayuki Okamoto Subject: Re: [PATCH 2/2] KVM: selftests: arm64: Add 52-bit VA guest modes Message-ID: References: <20260826-arm64-52bit-va-v1-0-14ec98211363@fujitsu.com> <20260826-arm64-52bit-va-v1-2-14ec98211363@fujitsu.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Fuad, On Fri, Sep 04, 2026 at 09:45:30AM +0100, Fuad Tabba wrote: > Hi Itaru, > > On Tue, 25 Aug 2026 at 22:18, Itaru Kitayama wrote: > ... > > diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/testing/selftests/kvm/lib/arm64/processor.c > > index 9108e14a9b5b..bcdf670c9eb8 100644 > > --- a/tools/testing/selftests/kvm/lib/arm64/processor.c > > +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c > > @@ -46,7 +46,7 @@ static u64 pud_index(struct kvm_vm *vm, gva_t gva) > > u64 mask = (1UL << (vm->page_shift - 3)) - 1; > > > > TEST_ASSERT(vm->mmu.pgtable_levels >= 4, > > - "Mode %d does not have at least 4 page table levels", > > + "Mode %d does not have >= 4 page table levels", > > Patch 1 added this string one commit earlier. Could it go in with the > final wording there? Surely, will fix in v2. > > ... > > > @@ -298,10 +304,14 @@ struct kvm_vm *____vm_create(struct vm_shape shape) > > > > /* Setup mode specific traits. */ > > switch (vm->mode) { > > + case VM_MODE_P52V52_4K: > > + vm->mmu.pgtable_levels = 5; > > + break; > > This is now the deepest mode, so page_fault_test.c's sizing is stale: > > * VM_MODE_P48V48_4K is the mode with most PT pages; let's use > * twice that just in case. > pt_size = 26 * guest_page_size; > > The margin still covers it. Could pt_size come from vm->mmu.pgtable_levels? I'm not the author of the page_fault_test.c for arm64, but so I'm guessing here; per the comment in the test, I dont think total number of levels determines pt_size, rather by the addresses prepared for the test. This stress test does not require high virtual addresses, though should we update the comment while at it? Thanks, Itaru. > > Cheers, > /fuad > > > > case VM_MODE_P52V48_4K: > > vm->mmu.pgtable_levels = 4; > > break; > > case VM_MODE_P52V48_64K: > > + case VM_MODE_P52V52_64K: > > vm->mmu.pgtable_levels = 3; > > break; > > case VM_MODE_P48V48_4K: > > @@ -322,6 +332,7 @@ struct kvm_vm *____vm_create(struct vm_shape shape) > > case VM_MODE_P48V48_16K: > > case VM_MODE_P40V48_16K: > > case VM_MODE_P36V48_16K: > > + case VM_MODE_P52V52_16K: > > vm->mmu.pgtable_levels = 4; > > break; > > case VM_MODE_P47V47_16K: > > > > -- > > 2.43.0 > > >