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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	Mark Brown <broonie@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/4] arm64/sysreg: Add VTCR_EL2 register
Date: Tue, 19 Aug 2025 09:54:29 +0530	[thread overview]
Message-ID: <bf78530c-e3e7-42b1-be7c-409d6427afda@arm.com> (raw)
In-Reply-To: <aKLw1jvwOo4wG64n@J2N7QTR9R3>



On 18/08/25 2:52 PM, Mark Rutland wrote:
> On Mon, Aug 18, 2025 at 10:27:59AM +0530, Anshuman Khandual wrote:
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index d2b40105eb41..f5a0a304f844 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -4910,6 +4910,63 @@ Field	1	PIE
>>  Field	0	PnCH
>>  EndSysreg
>>  
>> +Sysreg	VTCR_EL2	3	4	2	1	2
>> +Res0	63:46
>> +Field	45	HDBSS
>> +Field	44	HAFT
>> +Res0	43:42
>> +Field	41	TL0
>> +Field	40	GCSH
>> +Res0	39
>> +Field	38	D128
>> +Field	37	S2POE
>> +Field	36	S2PIE
>> +Field	35	TL1
>> +Field	34	AssuredOnly
>> +Field	33	SL2
>> +Field	32	DS
>> +Res1	31
>> +Field	30	NSA
>> +Field	29	NSW
>> +Field	28	HWU62
>> +Field	27	HWU61
>> +Field	26	HWU60
>> +Field	25	HWU59
>> +Res0	24:23
>> +Field	22	HD
>> +Field	21	HA
>> +Res0	20
>> +UnsignedEnum	19	VS
>> +	0b0	8BIT
>> +	0b1	16BIT
>> +EndEnum
> 
> You left TCR_EL1.AS as a single-bit 'Field', so please do the same here
> for consistency. I don't think there's much gained by making this any
> sort of enum.

But actually there is an use case in kvm_get_vtcr().

        /* Set the vmid bits */
        vtcr |= (get_vmid_bits(mmfr1) == 16) ?
                SYS_FIELD_PREP_ENUM(VTCR_EL2, VS, 16BIT) :
                SYS_FIELD_PREP_ENUM(VTCR_EL2, VS, 8BIT);

> 
>> +Field	18:16	PS
>> +UnsignedEnum	15:14	TG0
>> +		0b00	4K
>> +		0b01	64K
>> +		0b10	16K
>> +EndEnum
> 
> As with other patches, this is not ordered. Please use Enum.
> 
> Likewise for the other cases below.


Sure, will do the changes.
> 
> Mark.
> 
>> +UnsignedEnum	13:12	SH0
>> +		0b00	NONE
>> +		0b10	OUTER
>> +		0b11	INNER
>> +EndEnum
>> +UnsignedEnum	11:10	ORGN0
>> +	0b00	NC
>> +	0b01	WBWA
>> +	0b10	WT
>> +	0b11	WBnWA
>> +EndEnum
>> +UnsignedEnum	9:8	IRGN0
>> +	0b00	NC
>> +	0b01	WBWA
>> +	0b10	WT
>> +	0b11	WBnWA
>> +EndEnum
>> +Field	7:6	SL0
>> +Field	5:0	T0SZ
>> +EndSysreg
>> +
>>  SysregFields MAIR2_ELx
>>  Field	63:56	Attr7
>>  Field	55:48	Attr6
>> -- 
>> 2.25.1
>>
>>


  reply	other threads:[~2025-08-19  4:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-18  4:57 [PATCH 0/4] arm64/sysreg: Clean up TCR_XXX field macros Anshuman Khandual
2025-08-18  4:57 ` [PATCH 1/4] arm64/sysreg: Update TCR_EL1 register Anshuman Khandual
2025-08-18  9:11   ` Mark Rutland
2025-08-19  3:43     ` Anshuman Khandual
2025-08-18  4:57 ` [PATCH 2/4] arm64/sysreg: Replace TCR_EL1 field macros Anshuman Khandual
2025-08-18 15:46   ` Marc Zyngier
2025-08-19  6:46     ` Anshuman Khandual
2025-08-19  8:12       ` Marc Zyngier
2025-08-18  4:57 ` [PATCH 3/4] arm64/sysreg: Add TCR_EL2 register Anshuman Khandual
2025-08-18  9:17   ` Mark Rutland
2025-08-19  3:46     ` Anshuman Khandual
2025-08-18 15:43   ` Marc Zyngier
2025-08-19  5:58     ` Anshuman Khandual
2025-08-19  8:29       ` Marc Zyngier
2025-08-18  4:57 ` [PATCH 4/4] arm64/sysreg: Add VTCR_EL2 register Anshuman Khandual
2025-08-18  9:22   ` Mark Rutland
2025-08-19  4:24     ` Anshuman Khandual [this message]
2025-08-19  8:35       ` Marc Zyngier

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