From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3639B34CFCE for ; Wed, 22 Oct 2025 15:05:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761145531; cv=none; b=X3qHCf5aV6ih91pXfKI3tmQuCFqJWp85Cf9jf0v4TdA5K40HQOgt4oWf7m/vnlNDReOQhfqaIcaAsJ+G83Vs6F9y+DFoZQV4vWQT7JJFdKvDAJDlvzQBcJm3WkCPHR9tcHnbxGEahLYaKawPMvouhSAaw+r619D+GyCitYOKItk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761145531; c=relaxed/simple; bh=+SUhYDfPlXhJTf0EZe+qe3Cet5/03cMNLV35GCCCJB0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=X1wMJC9FrqSgC4DzjAuvYLBuR5nVm4HWigQKalSQn8F0V8s40mkYvE/DnfOICc6Udxu5i+/HBeiGtkz09LCEDzKkTN+3GaSqVcJ4UrweDSh8j4dpAuMqpTPS2VnUY4e3QRBpsBazIQZ+vmlGk84ogajvLgG2W9r/uv3bvhBpeVU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 789BD1063; Wed, 22 Oct 2025 08:05:19 -0700 (PDT) Received: from [10.1.197.1] (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 04A603F63F; Wed, 22 Oct 2025 08:05:24 -0700 (PDT) Message-ID: Date: Wed, 22 Oct 2025 16:05:23 +0100 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 04/23] perf: arm_pmuv3: Introduce method to partition the PMU To: Colton Lewis , kvm@vger.kernel.org Cc: Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Zenghui Yu , Mark Rutland , Shuah Khan , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org References: <20250714225917.1396543-1-coltonlewis@google.com> <20250714225917.1396543-5-coltonlewis@google.com> Content-Language: en-US From: Suzuki K Poulose In-Reply-To: <20250714225917.1396543-5-coltonlewis@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/07/2025 23:58, Colton Lewis wrote: > For PMUv3, the register field MDCR_EL2.HPMN partitiones the PMU > counters into two ranges where counters 0..HPMN-1 are accessible by > EL1 and, if allowed, EL0 while counters HPMN..N are only accessible by > EL2. > > Create module parameter reserved_host_counters to reserve a number of > counters for the host. This number is set at boot because the perf > subsystem assumes the number of counters will not change after the PMU > is probed. > > Introduce the function armv8pmu_partition() to modify the PMU driver's > cntr_mask of available counters to exclude the counters being reserved > for the guest and record reserved_guest_counters as the maximum > allowable value for HPMN. > > Due to the difficulty this feature would create for the driver running > in nVHE mode, partitioning is only allowed in VHE mode. In order to > support a partitioned on nVHE we'd need to explicitly disable guest > counters on every exit and reset HPMN to place all counters in the > first range. > > Signed-off-by: Colton Lewis > --- > arch/arm/include/asm/arm_pmuv3.h | 14 ++++++ > arch/arm64/include/asm/arm_pmuv3.h | 5 ++ > arch/arm64/include/asm/kvm_pmu.h | 6 +++ > arch/arm64/kvm/Makefile | 2 +- > arch/arm64/kvm/pmu-direct.c | 22 +++++++++ > drivers/perf/arm_pmuv3.c | 74 +++++++++++++++++++++++++++++- > include/linux/perf/arm_pmu.h | 1 + > 7 files changed, 121 insertions(+), 3 deletions(-) > create mode 100644 arch/arm64/kvm/pmu-direct.c > > diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h > index 2ec0e5e83fc9..49b1f2d7842d 100644 > --- a/arch/arm/include/asm/arm_pmuv3.h > +++ b/arch/arm/include/asm/arm_pmuv3.h > @@ -221,6 +221,10 @@ static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) > return false; > } > > +static inline bool kvm_pmu_partition_supported(void) > +{ > + return false; > +} > static inline bool kvm_set_pmuserenr(u64 val) > { > return false; > @@ -228,6 +232,11 @@ static inline bool kvm_set_pmuserenr(u64 val) > > static inline void kvm_vcpu_pmu_resync_el0(void) {} > > +static inline bool has_vhe(void) > +{ > + return false; > +} > + > /* PMU Version in DFR Register */ > #define ARMV8_PMU_DFR_VER_NI 0 > #define ARMV8_PMU_DFR_VER_V3P1 0x4 > @@ -242,6 +251,11 @@ static inline bool pmuv3_implemented(int pmuver) > pmuver == ARMV8_PMU_DFR_VER_NI); > } > > +static inline bool is_pmuv3p1(int pmuver) > +{ > + return pmuver >= ARMV8_PMU_DFR_VER_V3P1; > +} > + > static inline bool is_pmuv3p4(int pmuver) > { > return pmuver >= ARMV8_PMU_DFR_VER_V3P4; > diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h > index cf2b2212e00a..27c4d6d47da3 100644 > --- a/arch/arm64/include/asm/arm_pmuv3.h > +++ b/arch/arm64/include/asm/arm_pmuv3.h > @@ -171,6 +171,11 @@ static inline bool pmuv3_implemented(int pmuver) > pmuver == ID_AA64DFR0_EL1_PMUVer_NI); > } > > +static inline bool is_pmuv3p1(int pmuver) > +{ > + return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P1; > +} > + > static inline bool is_pmuv3p4(int pmuver) > { > return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4; > diff --git a/arch/arm64/include/asm/kvm_pmu.h b/arch/arm64/include/asm/kvm_pmu.h > index 6c961e877804..8a2ed02e157d 100644 > --- a/arch/arm64/include/asm/kvm_pmu.h > +++ b/arch/arm64/include/asm/kvm_pmu.h > @@ -46,6 +46,7 @@ struct arm_pmu_entry { > }; > > bool kvm_supports_guest_pmuv3(void); > +bool kvm_pmu_partition_supported(void); > #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS) > u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx); > void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val); > @@ -115,6 +116,11 @@ static inline bool kvm_supports_guest_pmuv3(void) > return false; > } > > +static inline bool kvm_pmu_partition_supported(void) > +{ > + return false; > +} > + > #define kvm_arm_pmu_irq_initialized(v) (false) > static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, > u64 select_idx) > diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile > index 86035b311269..7ce842217575 100644 > --- a/arch/arm64/kvm/Makefile > +++ b/arch/arm64/kvm/Makefile > @@ -23,7 +23,7 @@ kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ > vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \ > vgic/vgic-its.o vgic/vgic-debug.o vgic/vgic-v3-nested.o > > -kvm-$(CONFIG_HW_PERF_EVENTS) += pmu-emul.o pmu.o > +kvm-$(CONFIG_HW_PERF_EVENTS) += pmu-emul.o pmu-direct.o pmu.o > kvm-$(CONFIG_ARM64_PTR_AUTH) += pauth.o > kvm-$(CONFIG_PTDUMP_STAGE2_DEBUGFS) += ptdump.o > > diff --git a/arch/arm64/kvm/pmu-direct.c b/arch/arm64/kvm/pmu-direct.c > new file mode 100644 > index 000000000000..9423d6f65059 > --- /dev/null > +++ b/arch/arm64/kvm/pmu-direct.c > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2025 Google LLC > + * Author: Colton Lewis > + */ > + > +#include > + > +#include > + > +/** > + * kvm_pmu_partition_supported() - Determine if partitioning is possible > + * > + * Partitioning is only supported in VHE mode (with PMUv3, assumed > + * since we are in the PMUv3 driver) > + * > + * Return: True if partitioning is possible, false otherwise > + */ > +bool kvm_pmu_partition_supported(void) > +{ > + return has_vhe(); > +} > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index c2e3672e1228..294ccbdc3816 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -40,6 +40,12 @@ > #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC > #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED > > +static int reserved_host_counters __read_mostly = -1; > + > +module_param(reserved_host_counters, int, 0); > +MODULE_PARM_DESC(reserved_host_counters, > + "PMU Partition: -1 = No partition; +N = Reserve N counters for the host"); > + > /* > * ARMv8 Architectural defined events, not all of these may > * be supported on any given implementation. Unsupported events will > @@ -505,6 +511,11 @@ static void armv8pmu_pmcr_write(u64 val) > write_pmcr(val); > } > > +static u64 armv8pmu_pmcr_n_read(void) > +{ > + return FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read()); > +} > + > static int armv8pmu_has_overflowed(u64 pmovsr) > { > return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK); > @@ -1200,6 +1211,58 @@ struct armv8pmu_probe_info { > bool present; > }; > > +/** > + * armv8pmu_reservation_is_valid() - Determine if reservation is allowed > + * @host_counters: Number of host counters to reserve > + * > + * Determine if the number of host counters in the argument is an > + * allowed reservation, 0 to NR_COUNTERS inclusive. > + * > + * Return: True if reservation allowed, false otherwise > + */ > +static bool armv8pmu_reservation_is_valid(int host_counters) > +{ > + return host_counters >= 0 && > + host_counters <= armv8pmu_pmcr_n_read(); > +} > + > +/** > + * armv8pmu_partition() - Partition the PMU > + * @pmu: Pointer to pmu being partitioned > + * @host_counters: Number of host counters to reserve > + * > + * Partition the given PMU by taking a number of host counters to > + * reserve and, if it is a valid reservation, recording the > + * corresponding HPMN value in the hpmn_max field of the PMU and > + * clearing the guest-reserved counters from the counter mask. > + * > + * Return: 0 on success, -ERROR otherwise > + */ > +static int armv8pmu_partition(struct arm_pmu *pmu, int host_counters) > +{ > + u8 nr_counters; > + u8 hpmn; > + > + if (!armv8pmu_reservation_is_valid(host_counters)) > + return -EINVAL; > + > + nr_counters = armv8pmu_pmcr_n_read(); > + hpmn = nr_counters - host_counters; > + > + pmu->hpmn_max = hpmn; > + > + bitmap_clear(pmu->cntr_mask, 0, hpmn); > + bitmap_set(pmu->cntr_mask, hpmn, host_counters); > + clear_bit(ARMV8_PMU_CYCLE_IDX, pmu->cntr_mask); > + > + if (pmuv3_has_icntr()) > + clear_bit(ARMV8_PMU_INSTR_IDX, pmu->cntr_mask); > + > + pr_info("Partitioned PMU with HPMN %u", hpmn); > + > + return 0; > +} > + > static void __armv8pmu_probe_pmu(void *info) > { > struct armv8pmu_probe_info *probe = info; > @@ -1214,10 +1277,10 @@ static void __armv8pmu_probe_pmu(void *info) > > cpu_pmu->pmuver = pmuver; > probe->present = true; > + cpu_pmu->hpmn_max = -1; > > /* Read the nb of CNTx counters supported from PMNC */ > - bitmap_set(cpu_pmu->cntr_mask, > - 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); > + bitmap_set(cpu_pmu->cntr_mask, 0, armv8pmu_pmcr_n_read()); > > /* Add the CPU cycles counter */ > set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask); > @@ -1226,6 +1289,13 @@ static void __armv8pmu_probe_pmu(void *info) > if (pmuv3_has_icntr()) > set_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask); > > + if (reserved_host_counters >= 0) { > + if (kvm_pmu_partition_supported()) > + WARN_ON(armv8pmu_partition(cpu_pmu, reserved_host_counters)); Does this really warrant a WARN_ON ? Given we 1. This can be easily triggered by a user (e.g. with modprobe) 2. We gracefully handle it and init to a safe setting. A pr_warn is sufficient ? Otherwise looks good to me. Suzuki