From: Auger Eric <eric.auger@redhat.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
Christoffer Dall <christoffer.dall@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
kvm@vger.kernel.org, David Daney <david.daney@cavium.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Robert Richter <rrichter@cavium.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 24/31] arm64: Add MIDR values for Cavium cn83XX SoCs
Date: Tue, 30 May 2017 11:56:24 +0200 [thread overview]
Message-ID: <cd679ebf-4d34-9e4b-c53d-d583e73310f2@redhat.com> (raw)
In-Reply-To: <20170503104606.19342-25-marc.zyngier@arm.com>
Hi,
On 03/05/2017 12:45, Marc Zyngier wrote:
> From: David Daney <david.daney@cavium.com>
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
> ---
> arch/arm64/include/asm/cputype.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 0984d1b3a8f2..235e77d98261 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -86,6 +86,7 @@
>
> #define CAVIUM_CPU_PART_THUNDERX 0x0A1
> #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
> +#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
>
> #define BRCM_CPU_PART_VULCAN 0x516
>
> @@ -96,6 +97,7 @@
> #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
> #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> +#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
> #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
>
> #ifndef __ASSEMBLY__
>
next prev parent reply other threads:[~2017-05-30 9:56 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-03 10:45 [PATCH 00/31] arm64: KVM: Mediate access to GICv3 sysregs at EL2 Marc Zyngier
2017-05-03 10:45 ` [PATCH 01/31] arm64: KVM: Fix decoding of Rt/Rt2 when trapping AArch32 CP accesses Marc Zyngier
2017-05-03 10:45 ` [PATCH 02/31] arm64: KVM: Do not use stack-protector to compile EL2 code Marc Zyngier
2017-05-03 10:45 ` [PATCH 03/31] arm: KVM: Do not use stack-protector to compile HYP code Marc Zyngier
2017-05-03 10:45 ` [PATCH 04/31] KVM: arm/arm64: vgic-v2: Do not use Active+Pending state for a HW interrupt Marc Zyngier
2017-05-03 10:45 ` [PATCH 05/31] KVM: arm/arm64: vgic-v3: " Marc Zyngier
2017-05-03 10:45 ` [PATCH 06/31] KVM: arm/arm64: vgic-v3: Use PREbits to infer the number of ICH_APxRn_EL2 registers Marc Zyngier
2017-05-03 10:45 ` [PATCH 07/31] KVM: arm/arm64: vgic-v3: Add accessors for the " Marc Zyngier
2017-05-03 15:32 ` Mark Rutland
2017-05-03 15:58 ` Marc Zyngier
2017-05-30 16:17 ` Marc Zyngier
2017-05-30 16:42 ` Mark Rutland
2017-05-17 9:54 ` Auger Eric
2017-05-22 18:52 ` Marc Zyngier
2017-05-03 10:45 ` [PATCH 08/31] arm64: Add a facility to turn an ESR syndrome into a sysreg encoding Marc Zyngier
2017-05-03 15:35 ` Mark Rutland
2017-05-17 9:54 ` Auger Eric
2017-06-09 10:38 ` Catalin Marinas
2017-05-03 10:45 ` [PATCH 09/31] KVM: arm64: Make kvm_condition_valid32() accessible from EL2 Marc Zyngier
2017-05-17 9:54 ` Auger Eric
2017-05-03 10:45 ` [PATCH 10/31] KVM: arm64: vgic-v3: Add hook to handle guest GICv3 sysreg accesses at EL2 Marc Zyngier
2017-05-17 9:54 ` Auger Eric
2017-05-03 10:45 ` [PATCH 11/31] KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler Marc Zyngier
2017-05-17 15:39 ` Auger Eric
2017-05-03 10:45 ` [PATCH 12/31] KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Marc Zyngier
2017-05-17 15:39 ` Auger Eric
2017-05-03 10:45 ` [PATCH 13/31] KVM: arm64: vgic-v3: Add ICV_IAR1_EL1 handler Marc Zyngier
2017-05-18 7:41 ` Auger Eric
2017-05-22 17:52 ` Marc Zyngier
2017-05-23 7:22 ` Auger Eric
2017-05-23 9:26 ` Marc Zyngier
2017-05-03 10:45 ` [PATCH 14/31] KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Marc Zyngier
2017-05-30 7:48 ` Auger Eric
2017-05-30 14:24 ` Marc Zyngier
2017-05-31 6:33 ` Auger Eric
2017-05-31 6:46 ` Marc Zyngier
2017-05-31 7:26 ` Auger Eric
2017-05-31 7:54 ` Marc Zyngier
2017-05-03 10:45 ` [PATCH 15/31] KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler Marc Zyngier
2017-05-30 7:48 ` Auger Eric
2017-05-30 8:02 ` Auger Eric
2017-05-30 14:21 ` Marc Zyngier
2017-05-03 10:45 ` [PATCH 16/31] KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Marc Zyngier
2017-05-30 8:05 ` Auger Eric
2017-05-03 10:45 ` [PATCH 17/31] KVM: arm64: vgic-v3: Enable trapping of Group-1 system registers Marc Zyngier
2017-05-30 9:07 ` Auger Eric
2017-05-30 14:32 ` Marc Zyngier
2017-05-31 6:43 ` Auger Eric
2017-05-03 10:45 ` [PATCH 18/31] KVM: arm64: Enable GICv3 Group-1 sysreg trapping via command-line Marc Zyngier
2017-05-03 10:45 ` [PATCH 19/31] KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler Marc Zyngier
2017-05-30 9:48 ` Auger Eric
2017-05-03 10:45 ` [PATCH 20/31] KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler Marc Zyngier
2017-05-30 9:48 ` Auger Eric
2017-05-03 10:45 ` [PATCH 21/31] KVM: arm64: vgic-v3: Add misc Group-0 handlers Marc Zyngier
2017-05-30 9:48 ` Auger Eric
2017-05-03 10:45 ` [PATCH 22/31] KVM: arm64: vgic-v3: Enable trapping of Group-0 system registers Marc Zyngier
2017-05-30 9:48 ` Auger Eric
2017-05-03 10:45 ` [PATCH 23/31] KVM: arm64: Enable GICv3 Group-0 sysreg trapping via command-line Marc Zyngier
2017-05-03 10:45 ` [PATCH 24/31] arm64: Add MIDR values for Cavium cn83XX SoCs Marc Zyngier
2017-05-30 9:56 ` Auger Eric [this message]
2017-06-09 10:39 ` Catalin Marinas
2017-05-03 10:46 ` [PATCH 25/31] arm64: Add workaround for Cavium Thunder erratum 30115 Marc Zyngier
2017-05-30 9:56 ` Auger Eric
2017-06-09 10:43 ` Catalin Marinas
2017-05-03 10:46 ` [PATCH 26/31] KVM: arm64: vgic-v3: Add ICV_DIR_EL1 handler Marc Zyngier
2017-05-30 10:15 ` Auger Eric
2017-05-30 14:45 ` Marc Zyngier
2017-05-03 10:46 ` [PATCH 27/31] KVM: arm64: vgic-v3: Add ICV_RPR_EL1 handler Marc Zyngier
2017-05-30 10:16 ` Auger Eric
2017-05-03 10:46 ` [PATCH 28/31] KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler Marc Zyngier
2017-05-30 10:27 ` Auger Eric
2017-05-03 10:46 ` [PATCH 29/31] KVM: arm64: vgic-v3: Add ICV_PMR_EL1 handler Marc Zyngier
2017-05-30 10:34 ` Auger Eric
2017-05-03 10:46 ` [PATCH 30/31] KVM: arm64: Enable GICv3 common sysreg trapping via command-line Marc Zyngier
2017-05-30 9:56 ` Auger Eric
2017-05-30 14:41 ` Marc Zyngier
2017-05-03 10:46 ` [PATCH 31/31] KVM: arm64: vgic-v3: Log which GICv3 system registers are trapped Marc Zyngier
2017-05-30 9:56 ` Auger Eric
2017-05-09 0:05 ` [PATCH 00/31] arm64: KVM: Mediate access to GICv3 sysregs at EL2 David Daney
2017-05-09 17:39 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cd679ebf-4d34-9e4b-c53d-d583e73310f2@redhat.com \
--to=eric.auger@redhat.com \
--cc=catalin.marinas@arm.com \
--cc=christoffer.dall@linaro.org \
--cc=david.daney@cavium.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=rrichter@cavium.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox