From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07EA4C2BA19 for ; Wed, 15 Apr 2020 11:32:50 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 8BBA520737 for ; Wed, 15 Apr 2020 11:32:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8BBA520737 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0F2824B166; Wed, 15 Apr 2020 07:32:49 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vFqym7FQ4GMK; Wed, 15 Apr 2020 07:32:47 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id EA1714B10D; Wed, 15 Apr 2020 07:32:47 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 353D64B0FD for ; Wed, 15 Apr 2020 07:32:47 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AKLWpBuFVNEa for ; Wed, 15 Apr 2020 07:32:46 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 165364B0FA for ; Wed, 15 Apr 2020 07:32:46 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8470B1063; Wed, 15 Apr 2020 04:32:45 -0700 (PDT) Received: from [10.37.12.1] (unknown [10.37.12.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DCAB13F68F; Wed, 15 Apr 2020 04:32:42 -0700 (PDT) Subject: Re: [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] To: will@kernel.org References: <20200414213114.2378-1-will@kernel.org> <20200414213114.2378-8-will@kernel.org> <714f124c-7eb7-b750-e98c-63da64ddae75@arm.com> <20200415105843.GE12621@willie-the-truck> From: Suzuki K Poulose Message-ID: Date: Wed, 15 Apr 2020 12:37:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200415105843.GE12621@willie-the-truck> Content-Language: en-US Cc: saiprakash.ranjan@codeaurora.org, anshuman.khandual@arm.com, maz@kernel.org, linux-kernel@vger.kernel.org, dianders@chromium.org, catalin.marinas@arm.com, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 04/15/2020 11:58 AM, Will Deacon wrote: > On Wed, Apr 15, 2020 at 11:50:58AM +0100, Suzuki K Poulose wrote: >> On 04/14/2020 10:31 PM, Will Deacon wrote: >>> We don't need to be quite as strict about mismatched AArch32 support, >>> which is good because the friendly hardware folks have been busy >>> mismatching this to their hearts' content. >>> >>> * We don't care about EL2 or EL3 (there are silly comments concerning >>> the latter, so remove those) >>> >>> * EL1 support is gated by the ARM64_HAS_32BIT_EL1 capability and handled >>> gracefully when a mismatch occurs >>> >>> * EL1 support is gated by the ARM64_HAS_32BIT_EL0 capability and handled >> >> s/EL1/EL0 >> >>> gracefully when a mismatch occurs >>> >>> Relax the AArch32 checks to FTR_NONSTRICT. >> >> Agreed. We should do something similar for the features exposed by the >> ELF_HWCAP, of course in a separate series. > > Hmm, I didn't think we needed to touch the HWCAPs, as they're derived from > the sanitised feature register values. What am I missing? sorry, that was cryptic. I was suggesting to relax the ftr fields to NONSTRICT for the fields covered by ELF HWCAPs (and other CPU hwcaps). Suzuki _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm