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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ebe00sm16888782f8f.38.2025.05.13.08.29.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 May 2025 08:29:45 -0700 (PDT) Message-ID: Date: Tue, 13 May 2025 17:29:44 +0200 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: eric.auger@redhat.com Subject: Re: [PATCH v3 00/10] kvm/arm: Introduce a customizable aarch64 KVM host model To: Cornelia Huck , eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com References: <20250414163849.321857-1-cohuck@redhat.com> From: Eric Auger In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: n8641n_Kv62VoYCA7MZFrL05Brf5D3JAQIh-0aimIi8_1747150187 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, On 4/14/25 6:38 PM, Cornelia Huck wrote: > [This is on top of v5 of the ID register storage rework: > https://lore.kernel.org/qemu-devel/20250409144304.912325-1-cohuck@redhat.com/T/#t] > > It's been a while, but here's finally a respin of the series to make ID > registers configurable directly via the command line. > > Major changes from v2 include: > - split out the rework of ID register storage (see above) and rebased on top > of that > - hopefully improved the documentation > - fixed some bugs along the way (including output of the cpu model expansion > command, and compilation with HVF on) > > Decided against zeroing unknown registers; it's mostly a "dammed if you do, > dammed if you don't" situation as one case or the other will not quite work > as desired, even disregarding fields like AA64PFR1_EL1.MTE_frac where 0 > might indicate things we do not support. You'll need to be careful when > doing kernel updates and be explicit with configuring fields. This is not totally clear to me. Is it possible to come with examples and also derive some guidelines to avoid pitfalls? I guess this kind of aknowledgement can be scary. > > The current cpu properties stay as they are; we can work on converting them > to compatibility props once we have support for configuring the ID register > fields on the command line for the other accelerators (this is still KVM only.) At least what can we do to make sure they are not inconsistent and work well together. Looks like a must have before being non RFC. > > The FEAT_xxx features only support a subset of what we need to configure in > real life; for example, different AltraMax machines differ in CTR_EL0, which > is not covered by any FEAT_. It might make sense to provide them as syntactic > sugar on top. I agree that anyway we will need an ID reg field granularity for some real life cases. On top of that we shall try to build higher level props matching to features as requested by an overwhelming majority in earlier comments. > > We still have to deal with MIDR/REVIDR/AIDR differences by exploiting > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=d300b0168ea8fd5022a1413bd37ab63f4e5a7d4d > (in a different series.) Shameer, do you plan to contribute the qemu integration of this feature you developped on kernel side; or do you allow us to integrate it in this series? Thanks Eric > > I have not ignored the issue of named models on Arm, I just wanted to get the > base infrastructure into place first :) > > Real world example (migration Graviton 3 -> 4, thx to Sebastian): > > -cpu host,pauth=off,SYSREG_ID_AA64PFR0_EL1_SEL2=0,SYSREG_ID_AA64PFR0_EL1_EL0=1, > SYSREG_ID_AA64ISAR0_EL1_TLB=0,SYSREG_ID_AA64ISAR0_EL1_TS=0, > SYSREG_ID_AA64ISAR0_EL1_SM4=0,SYSREG_ID_AA64ISAR0_EL1_SM3=0, > SYSREG_ID_AA64ISAR1_EL1_SPECRES=0,SYSREG_ID_AA64ISAR1_EL1_SB=0, > SYSREG_ID_AA64ISAR1_EL1_FRINTTS=0,SYSREG_ID_AA64MMFR0_EL1_TGRAN4_2=1, > SYSREG_ID_AA64MMFR0_EL1_TGRAN16_2=1,SYSREG_ID_AA64MMFR0_EL1_TGRAN64_2=1 > > (not including handling MIDR differences, which is out of scope for this series) > > Code also available at > https://gitlab.com/cohuck/qemu/-/tree/arm-cpu-model-rfcv3?ref_type=heads > > > Cornelia Huck (5): > arm/cpu: Add generated sysreg properties > kvm: kvm_get_writable_id_regs > arm/cpu: accessors for writable id registers > arm-qmp-cmds: introspection for ID register props > arm/cpu-features: document ID reg properties > > Eric Auger (5): > arm/cpu: Add infra to handle generated ID register definitions > arm/cpu: Add sysreg properties generation > arm/kvm: Allow reading all the writable ID registers > arm/kvm: write back modified ID regs to KVM > arm/cpu: more customization for the kvm host cpu model > > docs/system/arm/cpu-features.rst | 104 +++- > scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++ > scripts/update-aarch64-sysreg-code.sh | 5 +- > target/arm/arm-qmp-cmds.c | 19 + > target/arm/cpu-custom.h | 60 +++ > target/arm/cpu-sysreg-properties.c | 713 ++++++++++++++++++++++++++ > target/arm/cpu-sysregs.h | 2 + > target/arm/cpu.c | 12 + > target/arm/cpu.h | 47 ++ > target/arm/cpu64.c | 24 +- > target/arm/kvm.c | 289 ++++++++++- > target/arm/kvm_arm.h | 26 +- > target/arm/meson.build | 1 + > target/arm/trace-events | 6 + > 14 files changed, 1617 insertions(+), 16 deletions(-) > create mode 100755 scripts/gen-cpu-sysreg-properties.awk > create mode 100644 target/arm/cpu-custom.h > create mode 100644 target/arm/cpu-sysreg-properties.c >