From: Zhou Wang <wangzhou1@hisilicon.com>
To: Arnd Bergmann <arnd@arndb.de>, Marc Zyngier <maz@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
<linux-arm-kernel@lists.infradead.org>, <kvmarm@lists.linux.dev>,
Yicong Yang <yangyccccc@gmail.com>, <prime.zeng@hisilicon.com>,
<xuwei5@huawei.com>
Subject: Re: [PATCH v7 5/7] arm64: Add support for FEAT_{LS64, LS64_V}
Date: Thu, 27 Nov 2025 11:51:37 +0800 [thread overview]
Message-ID: <e6cffbce-7cd4-3fe3-a9bd-935efedaebd0@hisilicon.com> (raw)
In-Reply-To: <f641d3f2-dac9-4a9e-92a4-0805e6561418@app.fastmail.com>
On 2025/11/18 15:36, Arnd Bergmann wrote:
> On Tue, Nov 18, 2025, at 03:31, Zhou Wang wrote:
>> On 2025/11/14 17:37, Arnd Bergmann wrote:
>>> On Fri, Nov 14, 2025, at 10:25, Zhou Wang wrote:
>>>> On 2025/11/14 0:26, Arnd Bergmann wrote:
>>>>>
>>>>> Are you using a particular device, or are you trying to enable
>>>>> the support in general? If you have a specific device you are
>>>>> working on, does it use the PASID data or not?
>>>>
>>>> Many thanks for your careful explanation! I got the pointer here.
>>>>
>>>> We have a real device in our SoC, which supports LS64B/ST64B/ST64BV.
>>>> For ST64BV, Our device just receives 64B data atomically, not interpret
>>>> it with PASID data.
>>>
>>> Ok, I see. So I assume this is either a kind of dedicated work queue
>>> where the IOMMU PASID is set up in advance for the user MMIO area,
>>
>> Yeah, it is something like you mentioned above. MMIO area is binded with
>> a work queue, a PASID is set up in advance for this work queue.
>
> Ok, thanks for confirming.
>
>>> or it is a device that does not do any DMA at all, correct?
>>>
>>> In this case, would the device also work correctly with ST64BV0 if
>>> the ACCDATA register is fixed to a value of zero and you can only
>>> use the upper 480 bits? Would it also work if there is an
>>> unpredictable value in ACCDATA that may match the PASID of another
>>> device used by the same process?
>>
>> We do not support ST64BV0, so above case will not happen. I think ST64BV0
>> will trigger a illegal instruction exception in our system.
>
> At least this does make it easier because on your system you would
> never run into a situation where you want to support both your
> internal device with st64bv and another device with st64bv0.
>
> The easiest setup I can think of that still supports your machine
> would look something like:
>
> - have the kernel choose between st64bv and st64bv0 at early boot,
> based on platform configuration, use st64bv0 by default if
> available in hardware and not disabled in EL3, EL2 or kernel
> command line.
> - Change pasid handling in iommu_sva_bind_device() so drivers
> have to explicitly request one of the modes before establishing
> a pasid, refuse this on incompatible systems, update the
> three existing callers (idxd, amdxdna, uacce) accordingly.
> - on systems with st64bv but no st64bv0, enable st64bv for
> all CPUs at boot time to avoid context switch overhead, but
> forbid mapping shared hardware workqueues into userspace.
> - postpone full support for st64bv0 until we have a device that
> actually uses this and can be tested. I think most of it is
> already there in the iommu code, but the ACCDATA setup needs
> to be integrated into the switch_mm()/__switch_to() code
> and possibly a trap handler like on x86.
Hi Arnd,
Sorry for late to reply, I double checked with our SoC and device
colleagues, currently only st64b has been used in our system.
So I think we could upstream FEAT_LS64 firstly as it seems easy
to be merged. After this, we continue to discuss FEAT_LS64V and
FEAT_LS64_ACCDATA solution if there is a real system need them.
Best,
Zhou
>
> In the current architecture, both FEAT_LS64_V and
> FEAT_LS64_ACCDATA are optional, so you can continue to
> produce CPUs that have the former but not the latter, and
> the logic above will keep that working. However this breaks
> if you ever want to support FEAT_LS64_ACCDATA in a later
> CPU but keep the existing driver working with st64bv.
>
> Arnd
> .
next prev parent reply other threads:[~2025-11-27 3:51 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-07 7:21 [PATCH v7 0/7] Add support for FEAT_{LS64, LS64_V} and related tests Zhou Wang
2025-11-07 7:21 ` [PATCH v7 1/7] KVM: arm64: Add exit to userspace on {LD,ST}64B* outside of memslots Zhou Wang
2025-11-07 11:48 ` Suzuki K Poulose
2025-11-07 11:49 ` Suzuki K Poulose
2025-11-11 2:12 ` Zhou Wang
2025-11-07 7:21 ` [PATCH v7 2/7] KVM: arm64: Add documentation for KVM_EXIT_ARM_LDST64B Zhou Wang
2025-11-07 7:21 ` [PATCH v7 3/7] KVM: arm64: Handle DABT caused by LS64* instructions on unsupported memory Zhou Wang
2025-11-07 7:21 ` [PATCH v7 4/7] arm64: Provide basic EL2 setup for FEAT_{LS64, LS64_V} usage at EL0/1 Zhou Wang
2025-11-07 7:21 ` [PATCH v7 5/7] arm64: Add support for FEAT_{LS64, LS64_V} Zhou Wang
2025-11-07 12:05 ` Suzuki K Poulose
2025-11-11 3:40 ` Zhou Wang
2025-11-11 11:15 ` Marc Zyngier
2025-11-13 14:40 ` Zhou Wang
2025-11-13 16:26 ` Arnd Bergmann
2025-11-14 9:25 ` Zhou Wang
2025-11-14 9:37 ` Arnd Bergmann
2025-11-18 2:31 ` Zhou Wang
2025-11-18 7:36 ` Arnd Bergmann
2025-11-27 3:51 ` Zhou Wang [this message]
2025-11-27 15:37 ` Arnd Bergmann
2025-12-05 6:47 ` Zhou Wang
2025-12-05 7:09 ` Arnd Bergmann
2025-11-07 7:21 ` [PATCH v7 6/7] KVM: arm64: Enable FEAT_{LS64, LS64_V} in the supported guest Zhou Wang
2025-11-07 18:53 ` Oliver Upton
2025-11-11 3:43 ` Zhou Wang
2025-11-07 7:21 ` [PATCH v7 7/7] kselftest/arm64: Add HWCAP test for FEAT_{LS64, LS64_V} Zhou Wang
2025-11-07 9:21 ` Arnd Bergmann
2025-11-07 9:23 ` [PATCH v7 0/7] Add support for FEAT_{LS64, LS64_V} and related tests Arnd Bergmann
2025-11-07 18:57 ` Oliver Upton
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