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Wed, 16 Oct 2024 19:36:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFbve1cFT+3/T9aIoiBUg75NmznGBWFLY7XVK/82tI9cQx42+1B5lOQ/CKFQ5WmsEJ1LXDSpQ== X-Received: by 2002:a17:903:40c6:b0:20b:5351:f69a with SMTP id d9443c01a7336-20d27f3fae7mr85434555ad.58.1729132594305; Wed, 16 Oct 2024 19:36:34 -0700 (PDT) Received: from [192.168.68.54] ([180.233.125.129]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1805b0afsm35119205ad.246.2024.10.16.19.36.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Oct 2024 19:36:33 -0700 (PDT) Message-ID: Date: Thu, 17 Oct 2024 12:36:27 +1000 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/7] arm64: cpufeature: discover CPU support for MPAM To: Joey Gouly , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: anshuman.khandual@arm.com, james.morse@arm.com, Marc Zyngier , Oliver Upton , Suzuki K Poulose , Zenghui Yu , Jing Zhang , Shameerali Kolothum Thodi , Catalin Marinas , Will Deacon References: <20241015133923.3910916-1-joey.gouly@arm.com> <20241015133923.3910916-4-joey.gouly@arm.com> From: Gavin Shan In-Reply-To: <20241015133923.3910916-4-joey.gouly@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/15/24 11:39 PM, Joey Gouly wrote: > From: James Morse > > ARMv8.4 adds support for 'Memory Partitioning And Monitoring' (MPAM) > which describes an interface to cache and bandwidth controls wherever > they appear in the system. > > Add support to detect MPAM. Like SVE, MPAM has an extra id register that > describes some more properties, including the virtualisation support, > which is optional. Detect this separately so we can detect > mismatched/insane systems, but still use MPAM on the host even if the > virtualisation support is missing. > > MPAM needs enabling at the highest implemented exception level, otherwise > the register accesses trap. The 'enabled' flag is accessible to lower > exception levels, but its in a register that traps when MPAM isn't enabled. > The cpufeature 'matches' hook is extended to test this on one of the > CPUs, so that firmware can emulate MPAM as disabled if it is reserved > for use by secure world. > > Secondary CPUs that appear late could trip cpufeature's 'lower safe' > behaviour after the MPAM properties have been advertised to user-space. > Add a verify call to ensure late secondaries match the existing CPUs. > > (If you have a boot failure that bisects here its likely your CPUs > advertise MPAM in the id registers, but firmware failed to either enable > or MPAM, or emulate the trap as if it were disabled) > > Signed-off-by: James Morse > Signed-off-by: Joey Gouly > --- > .../arch/arm64/cpu-feature-registers.rst | 2 + > arch/arm64/Kconfig | 20 ++++ > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/cpucaps.h | 2 + > arch/arm64/include/asm/cpufeature.h | 12 +++ > arch/arm64/include/asm/mpam.h | 32 ++++++ > arch/arm64/kernel/Makefile | 2 + > arch/arm64/kernel/cpufeature.c | 97 +++++++++++++++++++ > arch/arm64/kernel/cpuinfo.c | 4 + > arch/arm64/kernel/mpam.c | 6 ++ > arch/arm64/tools/cpucaps | 1 + > 11 files changed, 179 insertions(+) > create mode 100644 arch/arm64/include/asm/mpam.h > create mode 100644 arch/arm64/kernel/mpam.c > Reviewed-by: Gavin Shan