From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Fuad Tabba <tabba@google.com>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
maz@kernel.org, oliver.upton@linux.dev, will@kernel.org,
joey.gouly@arm.com, yuzenghui@huawei.com,
catalin.marinas@arm.com, vladimir.murzin@arm.com
Subject: Re: [PATCH v1 5/8] KVM: arm64: Fix Trace Buffer trap polarity for protected VMs
Date: Tue, 4 Nov 2025 18:03:26 +0000 [thread overview]
Message-ID: <fbe0d81a-c4c2-46f5-b809-1b74f9307c98@arm.com> (raw)
In-Reply-To: <CA+EHjTwPqm5wkmdGK60sn+S9BizK6LG5bSqWQLigsZVgXoJmUw@mail.gmail.com>
On 04/11/2025 17:56, Fuad Tabba wrote:
> Hi Suzuki,
>
> On Tue, 4 Nov 2025 at 17:50, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>
>> On 04/11/2025 12:59, Fuad Tabba wrote:
>>> The E2TB bits in MDCR_EL2 control trapping of Trace Buffer system
>>> register accesses. These accesses are trapped to EL2 when the bits are
>>> clear.
>>>
>>> The trap initialization logic for protected VMs in pvm_init_traps_mdcr()
>>> had the polarity inverted. When a guest did not support the ExtTrcBuff
>>> feature, the code was setting E2TB. This incorrectly disabled the trap,
>>> potentially allowing a protected guest to access registers for a feature
>>> it was not given.
>>>
>>> Fix this by inverting the operation.
>>>
>>> Fixes: f50758260bff ("KVM: arm64: Group setting traps for protected VMs by control register")
>>> Signed-off-by: Fuad Tabba <tabba@google.com>
>>> ---
>>> arch/arm64/kvm/hyp/nvhe/pkvm.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
>>> index 43bde061b65d..df0c59a29b35 100644
>>> --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
>>> +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
>>> @@ -118,7 +118,7 @@ static void pvm_init_traps_mdcr(struct kvm_vcpu *vcpu)
>>> val |= MDCR_EL2_TTRF;
>>>
>>> if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, ExtTrcBuff, IMP))
>>
>> Why are we checkin ExtTrcBuff ? Shouldn't that be TraceBuffer ?
>
> This is an existing bug that needs to be fixed. Thank for spotting it.
>
>>> - val |= MDCR_EL2_E2TB_MASK;
>>> + val &= ~MDCR_EL2_E2TB_MASK;
>> This looks correct to me.
>
> I don't thin it's correct. E2TB traps when clear, not set:
> https://developer.arm.com/documentation/ddi0601/2025-09/AArch64-Registers/MDCR-EL2--Monitor-Debug-Configuration-Register--EL2-
I meant your change to val looks correct.
Suzuki
>
>> Suzuki
>>
>>>
>>> /* Trap Debug Communications Channel registers */
>>> if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, FGT, IMP))
>>
>>
next prev parent reply other threads:[~2025-11-04 18:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 12:58 [PATCH v1 0/8] KVM: arm64: Fixes for guest CPU feature trapping and enabling Fuad Tabba
2025-11-04 12:58 ` [PATCH v1 1/8] KVM: arm64: Route MOPS exceptions to EL2 when guest lacks support Fuad Tabba
2025-11-04 13:44 ` Joey Gouly
2025-11-04 13:49 ` Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 2/8] KVM: arm64: Trap access to ALLINT if FEAT_NMI not supported by the guest Fuad Tabba
2025-11-04 15:15 ` Marc Zyngier
2025-11-04 15:30 ` Fuad Tabba
2025-11-04 17:22 ` Marc Zyngier
2025-11-04 17:30 ` Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 3/8] KVM: arm64: Enable LS64 instructions when supported by guest Fuad Tabba
2025-11-04 15:26 ` Marc Zyngier
2025-11-04 15:31 ` Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 4/8] KVM: arm64: Refactor vcpu_set_hcrx() to reduce indentation Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 5/8] KVM: arm64: Fix Trace Buffer trap polarity for protected VMs Fuad Tabba
2025-11-04 17:50 ` Suzuki K Poulose
2025-11-04 17:56 ` Fuad Tabba
2025-11-04 18:03 ` Suzuki K Poulose [this message]
2025-11-04 19:04 ` Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 6/8] KVM: arm64: Fix MTE flag initialization " Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 7/8] KVM: arm64: Prevent host from managing timer offsets " Fuad Tabba
2025-11-04 12:59 ` [PATCH v1 8/8] KVM: arm64: Define FAR_MASK for faulting IPA offset Fuad Tabba
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