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Tue, 2 Jun 2020 05:44:48 +0000 (UTC) Received: from localhost.localdomain (vpn2-54-70.bne.redhat.com [10.64.54.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8D7375D9C9; Tue, 2 Jun 2020 05:44:45 +0000 (UTC) Subject: Re: [PATCH RFCv2 9/9] arm64: Support async page fault To: Paolo Bonzini , Marc Zyngier References: <20200508032919.52147-1-gshan@redhat.com> <20200508032919.52147-10-gshan@redhat.com> <81adf013-3de7-23e6-7648-8aec821b033c@redhat.com> <8ab64c6a-582b-691d-79ab-21cdc0455cd3@redhat.com> <6a4a82a4-af01-98c2-c854-9199f55f7bd3@redhat.com> <6965aaf641a23fab64fbe2ceeb790272@kernel.org> <4337cca152df47c93d96e092189a0e36@kernel.org> <5c72c597-732e-7dbf-d056-665674ec1792@redhat.com> From: Gavin Shan Message-ID: Date: Tue, 2 Jun 2020 15:44:42 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <5c72c597-732e-7dbf-d056-665674ec1792@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Cc: catalin.marinas@arm.com, linux-kernel@vger.kernel.org, shan.gavin@gmail.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list Reply-To: Gavin Shan List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, Paolo, On 6/1/20 7:21 PM, Paolo Bonzini wrote: > On 31/05/20 14:44, Marc Zyngier wrote: >>> >>> Is there an ARM-approved way to reuse the S2 fault syndromes to detect >>> async page faults? >> >> It would mean being able to set an ESR_EL2 register value into ESR_EL1, >> and there is nothing in the architecture that would allow that, > > I understand that this is not what you want to do and I'm not proposing > it, but I want to understand this better: _in practice_ do CPUs check > closely what is written in ESR_EL1? > > In any case, the only way to implement this, it seems to me, would be a > completely paravirtualized exception vector that doesn't use ESR at all. > > On the other hand, for the page ready (interrupt) side assigning a PPI > seems complicated but doable. > Marc suggested to use SDEI in another reply. I think it might be the appropriate way to deliver page-not-present. To some extent, it could be regarded as exception, which doesn't use ESR at all. It matches with what Paolo is thinking of: paravirtualized exception vector that doesn't use ESR at all. However, it seems it's not supported in kvm-arm yet. So I assume it needs to be developed from scratch. Marc, could you please help to confirm? Thanks in advance. I agree with Paolo PPI (interrupt) might be the best way to deliver page-ready currently. I don't think SDEI is suitable because there are no big difference between SDEI and currently used DABT injection to some extent. With SDEI, We will have the issues we are facing. For example, some critical code section isn't safe to receive SDEI if I'm correct. Thanks, Gavin [...] _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm