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Wed, 9 Sep 2020 08:43:50 +0000 (UTC) Received: from EX13D20UWC001.ant.amazon.com (10.43.162.244) by EX13MTAUWC001.ant.amazon.com (10.43.162.135) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Sep 2020 08:43:49 +0000 Received: from Alexanders-MacBook-Air.local (10.43.162.55) by EX13D20UWC001.ant.amazon.com (10.43.162.244) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Sep 2020 08:43:46 +0000 Subject: Re: [PATCH v2] KVM: arm64: Allow to limit number of PMU counters To: Andrew Jones References: <20200908205730.23898-1-graf@amazon.com> <20200909062534.zsqadaeewfeqsgsj@kamzik.brq.redhat.com> From: Alexander Graf Message-ID: Date: Wed, 9 Sep 2020 10:43:41 +0200 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.16; rv:78.0) Gecko/20100101 Thunderbird/78.2.1 MIME-Version: 1.0 In-Reply-To: <20200909062534.zsqadaeewfeqsgsj@kamzik.brq.redhat.com> Content-Language: en-US X-Originating-IP: [10.43.162.55] X-ClientProxiedBy: EX13D17UWC003.ant.amazon.com (10.43.162.206) To EX13D20UWC001.ant.amazon.com (10.43.162.244) X-Mailman-Approved-At: Wed, 09 Sep 2020 04:46:23 -0400 Cc: kvm@vger.kernel.org, Marc Zyngier , linux-arm-kernel@lists.infradead.org, Robin Murphy , kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hey Drew! On 09.09.20 08:25, Andrew Jones wrote: > > On Tue, Sep 08, 2020 at 10:57:30PM +0200, Alexander Graf wrote: >> We currently pass through the number of PMU counters that we have available >> in hardware to guests. So if my host supports 10 concurrently active PMU >> counters, my guest will be able to spawn 10 counters as well. >> >> This is undesireable if we also want to use the PMU on the host for >> monitoring. In that case, we want to split the PMU between guest and >> host. >> >> To help that case, let's add a PMU attr that allows us to limit the number >> of PMU counters that we expose. With this patch in place, user space can >> keep some counters free for host use. > > Hi Alex, > > Is there any reason to use the device API instead of just giving the user > control over the necessary PMCR_EL0 bits through set/get-one-reg? I mostly used the attr interface because I was in that particular mental mode after looking at the filtering bits :). Today, the PMCR_EL0 register gets reset implicitly on every vcpu reset call. How would we persist the counter field across resets? Would we in the first place? I'm slightly hazy how the ONE_REG API would look like here. Do you have recommendations? Alex Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm