Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: missing M3 and M4 from has_vgic_v3 KVM capability array
--

commit adcc2ca70d0cb38584f5c01ccf8a91f249b43c44
Author: Michael Reeves <michael.reeves077@gmail.com>

arm64: Apply existing Apple CPU workarounds to M3 and M4

Add M3, M3 Pro, M3 Max and base M4 to apple_cpus so they receive the
existing PMU trap and broken SEIS workarounds needed by KVM.

> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index e0c09402540ce..8a7703b86f3ef 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -288,6 +288,14 @@ static const struct midr_range apple_cpus[] = {
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_PRO),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_PRO),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_MAX),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_MAX),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_ECORE),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_PCORE),
>  	{},
>  };

[Severity: High]
Does this commit also need to update the has_vgic_v3 array in
can_trap_icv_dir_el1() in arch/arm64/kernel/cpufeature.c with these M3 and M4
MIDRs?

Because Apple SoCs use AIC instead of a standard physical GIC, they lack the
ARM64_HAS_GICV3_CPUIF CPU capability. To use the hardware vGIC's TDIR (Trap
DIR) feature on Apple Silicon, KVM relies on the has_vgic_v3 array in
can_trap_icv_dir_el1().

Since M3 and M4 are omitted from has_vgic_v3, can_trap_icv_dir_el1() returns
false on M3 and M4, clearing the ARM64_HAS_ICH_HCR_EL2_TDIR capability.

When this capability is missing, KVM's fallback path in
kvm_compute_ich_hcr_trap_bits() forces common_trap = true (setting the
ICH_HCR_EL2.TC bit). This traps all guest GICv3 system register accesses to
EL2 for software emulation, causing a catastrophic performance degradation
for interrupt-heavy virtualization workloads.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com?part=2