From: "Jürgen Groß" <jgross@suse.com>
To: "Xin Li (Intel)" <xin@zytor.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org,
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netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org
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dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com,
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dapeng1.mi@linux.intel.com
Subject: Re: [PATCH v3 10/14] x86/xen/msr: Remove pmu_msr_{read,write}()
Date: Fri, 25 Apr 2025 12:08:36 +0200 [thread overview]
Message-ID: <04d47f21-6183-42d5-bc18-f23a8c3c2009@suse.com> (raw)
In-Reply-To: <20250425083442.2390017-11-xin@zytor.com>
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On 25.04.25 10:34, Xin Li (Intel) wrote:
> As pmu_msr_{read,write}() are now wrappers of pmu_msr_chk_emulated(),
> remove them and use pmu_msr_chk_emulated() directly.
>
> As pmu_msr_chk_emulated() could easily return false in the cases where
> it would set *emul to false, remove the "emul" argument and use the
> return value instead.
>
> While at it, convert the data type of MSR index to u32 in functions
> called in pmu_msr_chk_emulated().
>
> Suggested-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> Suggested-by: Juergen Gross <jgross@suse.com>
> Signed-off-by: Xin Li (Intel) <xin@zytor.com>
> ---
>
> Change in v3:
> *) Remove the "emul" argument of pmu_msr_chk_emulated() (Juergen Gross).
> ---
> arch/x86/xen/enlighten_pv.c | 15 ++++++++-------
> arch/x86/xen/pmu.c | 30 ++++++------------------------
> arch/x86/xen/xen-ops.h | 3 +--
> 3 files changed, 15 insertions(+), 33 deletions(-)
>
> diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
> index 61e51a970f3c..528a2f4df050 100644
> --- a/arch/x86/xen/enlighten_pv.c
> +++ b/arch/x86/xen/enlighten_pv.c
> @@ -1090,7 +1090,7 @@ static u64 xen_do_read_msr(unsigned int msr, int *err)
> {
> u64 val = 0; /* Avoid uninitialized value for safe variant. */
>
> - if (pmu_msr_read_emulated(msr, &val))
> + if (pmu_msr_chk_emulated(msr, &val, true))
> return val;
>
> if (err)
> @@ -1162,12 +1162,13 @@ static void xen_do_write_msr(unsigned int msr, unsigned int low,
> default:
> val = (u64)high << 32 | low;
>
> - if (!pmu_msr_write_emulated(msr, val)) {
> - if (err)
> - *err = native_write_msr_safe(msr, low, high);
> - else
> - native_write_msr(msr, low, high);
> - }
> + if (pmu_msr_chk_emulated(msr, &val, false))
> + return;
> +
> + if (err)
> + *err = native_write_msr_safe(msr, low, high);
> + else
> + native_write_msr(msr, low, high);
> }
> }
>
> diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
> index b6557f2d1a2e..6bee83018694 100644
> --- a/arch/x86/xen/pmu.c
> +++ b/arch/x86/xen/pmu.c
> @@ -128,7 +128,7 @@ static inline uint32_t get_fam15h_addr(u32 addr)
> return addr;
> }
>
> -static inline bool is_amd_pmu_msr(unsigned int msr)
> +static bool is_amd_pmu_msr(u32 msr)
> {
> if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
> boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
> @@ -194,8 +194,7 @@ static bool is_intel_pmu_msr(u32 msr_index, int *type, int *index)
> }
> }
>
> -static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
> - int index, bool is_read)
> +static bool xen_intel_pmu_emulate(u32 msr, u64 *val, int type, int index, bool is_read)
> {
> uint64_t *reg = NULL;
> struct xen_pmu_intel_ctxt *ctxt;
> @@ -257,7 +256,7 @@ static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
> return false;
> }
>
> -static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
> +static bool xen_amd_pmu_emulate(u32 msr, u64 *val, bool is_read)
> {
> uint64_t *reg = NULL;
> int i, off = 0;
> @@ -298,33 +297,16 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
> return false;
> }
>
> -static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
> - bool *emul)
> +bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read)
> {
> int type, index = 0;
>
> if (is_amd_pmu_msr(msr))
> - *emul = xen_amd_pmu_emulate(msr, val, is_read);
> + return xen_amd_pmu_emulate(msr, val, is_read);
> else if (is_intel_pmu_msr(msr, &type, &index))
> - *emul = xen_intel_pmu_emulate(msr, val, type, index, is_read);
> + return xen_intel_pmu_emulate(msr, val, type, index, is_read);
> else
Can you please remove the two "else" instances above? With directly returning
form the "if" clause they are no longer needed.
With that you can add my:
Reviewed-by: Juergen Gross <jgross@suse.com>
Juergen
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next prev parent reply other threads:[~2025-04-25 10:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-25 8:34 [PATCH v3 00/14] MSR code cleanup part one Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 01/14] x86/msr: Move rdtsc{,_ordered}() to <asm/tsc.h> Xin Li (Intel)
2025-04-25 15:45 ` Ilpo Järvinen
2025-04-26 7:27 ` Xin Li
2025-04-26 13:45 ` Ilpo Järvinen
2025-04-25 8:34 ` [PATCH v3 02/14] x86/msr: Remove rdpmc() Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 03/14] x86/msr: Rename rdpmcl() to rdpmc() Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 04/14] x86/msr: Convert the rdpmc() macro into an always inline function Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 05/14] x86/msr: Return u64 consistently in Xen PMC read functions Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 06/14] x86/msr: Convert __wrmsr() uses to native_wrmsr{,q}() uses Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 07/14] x86/msr: Add the native_rdmsrq() helper Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 08/14] x86/msr: Convert __rdmsr() uses to native_rdmsrq() uses Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 09/14] x86/xen/msr: Remove calling native_{read,write}_msr{,_safe}() in pmu_msr_{read,write}() Xin Li (Intel)
2025-04-25 9:55 ` Jürgen Groß
2025-04-27 9:21 ` Mi, Dapeng
2025-04-27 9:26 ` Xin Li
2025-04-25 8:34 ` [PATCH v3 10/14] x86/xen/msr: Remove pmu_msr_{read,write}() Xin Li (Intel)
2025-04-25 10:08 ` Jürgen Groß [this message]
2025-04-26 7:40 ` Xin Li
2025-04-25 8:34 ` [PATCH v3 11/14] x86/xen/msr: Remove the error pointer argument from set_seg() Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 12/14] x86/pvops/msr: refactor pv_cpu_ops.write_msr{,_safe}() Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 13/14] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrq(msr, low) Xin Li (Intel)
2025-04-25 8:34 ` [PATCH v3 14/14] x86/msr: Change the function type of native_read_msr_safe() Xin Li (Intel)
2025-04-25 12:52 ` [PATCH v3 00/14] MSR code cleanup part one Peter Zijlstra
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