From: Ben Cheatham <benjamin.cheatham@amd.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: rafael@kernel.org, dan.j.williams@intel.com,
linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
bhelgaas@google.com, yazen.ghannam@amd.com
Subject: Re: [PATCH v5 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support
Date: Wed, 27 Sep 2023 10:31:15 -0500 [thread overview]
Message-ID: <0ee93e94-8a1a-8b4e-43ed-725a2fc9510a@amd.com> (raw)
In-Reply-To: <20230926202249.GA425563@bhelgaas>
On 9/26/23 3:22 PM, Bjorn Helgaas wrote:
> On Mon, Sep 25, 2023 at 03:01:26PM -0500, Ben Cheatham wrote:
>> Add support for CXL EINJ error types for CXL 1.1 hosts added in ACPI
>> v6.5. Because these error types target memory-mapped CXL 1.1 compliant
>> downstream ports and not physical (normal/persistent) memory, these
>> error types are not currently allowed through the memory range
>> validation done by the EINJ driver.
>>
>> The MMIO address of a CXL 1.1 downstream port can be found in the
>> cxl_rcrb_addr file in the corresponding dport directory under
>> /sys/bus/cxl/devices/portX. CXL 1.1 error types follow the same
>> procedure as a memory error type, but with param1 set to the
>> downstream port MMIO address.
>>
>> Example usage:
>> $ cd /sys/kernel/debug/apei/einj
>> $ cat available_error_type
>> 0x00000008 Memory Correctable
>> 0x00000010 Memory Uncorrectable non-fatal
>> 0x00000020 Memory Uncorrectable fatal
>> 0x00000040 PCI Express Correctable
>> 0x00000080 PCI Express Uncorrectable non-fatal
>> 0x00000100 PCI Express Uncorrectable fatal
>> 0x00008000 CXL.mem Protocol Correctable
>> 0x00020000 CXL.mem Protocol Uncorrectable fatal
>> $ echo 0x8000 > error_type
>> $ echo 0xfffffffffffff000 > param2
>> $ echo 0x2 > flags
>> $ cat /sys/bus/cxl/devices/portX/dportY/cxl_rcrb_addr
>> 0xb2f00000
>> $ echo 0xb2f00000 > param1
>
> It seems sort of unpleasant to expose the physical base address of the
> RCRB. Is there any way to use a device address or other logical
> identifier instead and keep the actual MMIO address internal? E.g., a
> PCI device has a <domain>:<bus>:<device>.<function> address. I assume
> CXL addresses would look similar?
>
I have the MMIO address of the dport exposed here because the ACPI spec
says that the address is expected for CXL 1.1 errors and I wanted to match
the spec. For CXL 2.0 errors the SBDF is expected as you described.
>> $ echo 1 > error_inject
>> ...
>
>> +static int is_valid_cxl_addr(u64 addr)
>
> Maybe the function name should include a hint that this should be an
> RCRB address? But I don't claim to know the CXL architecture or
> nomenclature.
>
Good point, if I keep this function in v6 I'll make the name more
descriptive.
> Bjorn
next prev parent reply other threads:[~2023-09-27 15:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 20:01 [PATCH v5 0/3] CXL, ACPI, APEI, EINJ: Update EINJ for CXL 1.1 error types Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev Ben Cheatham
2023-09-26 10:50 ` Jonathan Cameron
2023-09-26 16:00 ` Ben Cheatham
2023-09-26 20:23 ` Bjorn Helgaas
2023-09-27 15:30 ` Ben Cheatham
2023-09-26 21:15 ` Dan Williams
2023-09-27 15:31 ` Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support Ben Cheatham
2023-09-26 11:04 ` Jonathan Cameron
2023-09-26 16:00 ` Ben Cheatham
2023-09-26 20:22 ` Bjorn Helgaas
2023-09-27 15:31 ` Ben Cheatham [this message]
2023-09-26 21:36 ` Dan Williams
2023-09-27 15:32 ` Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 3/3] ACPI, APEI, EINJ: Update EINJ documentation Ben Cheatham
2023-09-26 11:05 ` Jonathan Cameron
2023-09-26 16:00 ` Ben Cheatham
2023-09-26 20:24 ` Bjorn Helgaas
2023-09-27 15:31 ` Ben Cheatham
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