From: "David E. Box" <david.e.box@linux.intel.com>
To: Christoph Hellwig <hch@lst.de>,
Mario Limonciello <mario.limonciello@amd.com>
Cc: Keith Busch <kbusch@kernel.org>, Jens Axboe <axboe@fb.com>,
Sagi Grimberg <sagi@grimberg.me>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"open list:NVM EXPRESS DRIVER" <linux-nvme@lists.infradead.org>,
linux-acpi@vger.kernel.org, rrangel@chromium.org,
Shyam-sundar.S-k@amd.com, Alexander.Deucher@amd.com,
prike.liang@amd.com, Shyjumon N <shyjumon.n@intel.com>,
Jon Derrick <jonathan.derrick@intel.com>
Subject: Re: [PATCH v3 1/2] nvme: Look for StorageD3Enable on companion ACPI device instead
Date: Tue, 01 Jun 2021 12:12:26 -0700 [thread overview]
Message-ID: <108f45a7c73d3ae571ee518c33dc793f36c1ffd2.camel@linux.intel.com> (raw)
In-Reply-To: <20210531064655.GA1417@lst.de>
On Mon, 2021-05-31 at 08:46 +0200, Christoph Hellwig wrote:
> On Fri, May 28, 2021 at 11:02:34AM -0500, Mario Limonciello wrote:
> > The documentation around the StorageD3Enable property hints that it
> > should be made on the PCI device. This is where newer AMD systems
> > set
> > the property and it's required for S0i3 support.
> >
> > So rather than look for nodes of the root port only present on
> > Intel
> > systems, switch to the companion ACPI device for all systems.
> > David Box from Intel indicated this should work on Intel as well.
>
> I think we need to wait for the confirmation from David.
I've tested one configuration remotely already and it works. I've got
one more to test. I'll know by tomorrow.
David
next prev parent reply other threads:[~2021-06-01 19:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-28 16:02 [PATCH v3 1/2] nvme: Look for StorageD3Enable on companion ACPI device instead Mario Limonciello
2021-05-31 6:46 ` Christoph Hellwig
2021-06-01 5:22 ` N, Shyjumon
2021-06-01 15:15 ` Limonciello, Mario
2021-06-02 22:49 ` David E. Box
2021-06-01 19:12 ` David E. Box [this message]
2021-06-03 7:17 ` Christoph Hellwig
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