* Radeon PM Support
@ 2004-07-29 22:14 Andrew Barr
[not found] ` <1091139240.26511.9.camel-0uShlLfvWR/1N/xxgP7OLA@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Andrew Barr @ 2004-07-29 22:14 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
I just bought a Radeon 7000 video card on-line. What is the status of
and plans for power management support for this card? I read
Documentation/power/video.txt, and it says that I can't have framebuffer
console. That could be a problem as I use bootsplash. It also says I
need a patched X server. My Google search turned up a page concerning
S3/Radeon that says the patch is no longer necessary (I can't find the
URL at the moment, sorry). Any thoughts, tips, tricks, etc. would be
greatly appreciated.
Regards,
Andrew Barr
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* Re: Radeon PM Support
[not found] ` <20040730141028.GE21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
@ 2004-07-30 13:31 ` Andrew Barr
2004-07-30 14:27 ` wwp
2004-08-06 20:10 ` Ow Mun Heng
2 siblings, 0 replies; 54+ messages in thread
From: Andrew Barr @ 2004-07-30 13:31 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
On Fri, 2004-07-30 at 14:10, Micha Feigin wrote:
[...]
> I am not sure about the current state of things. AFAIK the problem was
> with dri suspend support for radeon, and at the time at least, the card
> was reset on VT switch to enable suspend. IIRC the patch was
> incorporated into main the main tree quite some time ago.
>
> I have no experience with S3 suspend (my laptop doesn't seem to support
> it) but it does suspend with swsusp2 if I switch VT.
Thanks to everyone for their responses. I won't be able to try anything
out for a week or so because the card is in the mail still, but this
gives me a good idea of what to expect when I do get it. Thanks again.
Andrew
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* Re: Radeon PM Support
[not found] ` <1091139240.26511.9.camel-0uShlLfvWR/1N/xxgP7OLA@public.gmane.org>
@ 2004-07-30 14:10 ` Micha Feigin
[not found] ` <20040730141028.GE21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Micha Feigin @ 2004-07-30 14:10 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
On Thu, Jul 29, 2004 at 10:14:00PM +0000, Andrew Barr wrote:
> I just bought a Radeon 7000 video card on-line. What is the status of
> and plans for power management support for this card? I read
> Documentation/power/video.txt, and it says that I can't have framebuffer
> console. That could be a problem as I use bootsplash. It also says I
> need a patched X server. My Google search turned up a page concerning
> S3/Radeon that says the patch is no longer necessary (I can't find the
> URL at the moment, sorry). Any thoughts, tips, tricks, etc. would be
> greatly appreciated.
>
I am not sure about the current state of things. AFAIK the problem was
with dri suspend support for radeon, and at the time at least, the card
was reset on VT switch to enable suspend. IIRC the patch was
incorporated into main the main tree quite some time ago.
I have no experience with S3 suspend (my laptop doesn't seem to support
it) but it does suspend with swsusp2 if I switch VT.
> Regards,
> Andrew Barr
>
>
>
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> _______________________________________________
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* Re: Radeon PM Support
[not found] ` <20040730141028.GE21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
2004-07-30 13:31 ` Andrew Barr
@ 2004-07-30 14:27 ` wwp
[not found] ` <20040730162756.4f300a5c-bi+AKbBUZKZeoWH0uzbU5w@public.gmane.org>
2004-08-06 20:10 ` Ow Mun Heng
2 siblings, 1 reply; 54+ messages in thread
From: wwp @ 2004-07-30 14:27 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Hello Micha,
On Fri, 30 Jul 2004 17:10:28 +0300 Micha Feigin <michf-+lLcF8/aw9x6auLlOhE+pQ@public.gmane.org> wrote:
[snip]
> I am not sure about the current state of things. AFAIK the problem was
> with dri suspend support for radeon, and at the time at least, the card
> was reset on VT switch to enable suspend. IIRC the patch was
> incorporated into main the main tree quite some time ago.
>
> I have no experience with S3 suspend (my laptop doesn't seem to support
> it) but it does suspend with swsusp2 if I switch VT.
I m just curious: do you switch to VT or do you close X and return to console
(or even do `init 2`)?
Regards,
--
wwp
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* Re: Radeon PM Support
[not found] ` <20040730162756.4f300a5c-bi+AKbBUZKZeoWH0uzbU5w@public.gmane.org>
@ 2004-07-30 19:00 ` Micha Feigin
[not found] ` <20040730190047.GH21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Micha Feigin @ 2004-07-30 19:00 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
On Fri, Jul 30, 2004 at 04:27:56PM +0200, wwp wrote:
> Hello Micha,
>
>
> On Fri, 30 Jul 2004 17:10:28 +0300 Micha Feigin <michf-+lLcF8/aw9x6auLlOhE+pQ@public.gmane.org> wrote:
>
> [snip]
> > I am not sure about the current state of things. AFAIK the problem was
> > with dri suspend support for radeon, and at the time at least, the card
> > was reset on VT switch to enable suspend. IIRC the patch was
> > incorporated into main the main tree quite some time ago.
> >
> > I have no experience with S3 suspend (my laptop doesn't seem to support
> > it) but it does suspend with swsusp2 if I switch VT.
>
> I m just curious: do you switch to VT or do you close X and return to console
> (or even do `init 2`)?
>
I have a script that basically does
VT=`fgconsole`
chvt 9
echo 4 > /proc/acpi/sleep (or whatever sleep command you use)
chvt $VT
This changes to a console terminal before suspend, suspends, and on
resume switches back to X. This will also reset the card properly. Its
actually a mach64 and not a radeon, but I ported the relevant portions
of the radeon dri driver PM to the mach64. Note though that mach64
needs no kernel PM support, its all done on the X side (didn't find out
yet how to do it on the kernel side, although I hope to do that when I
have them time, that would save the VT switch).
>
> Regards,
>
> --
> wwp
>
>
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* Re: Radeon PM Support
[not found] ` <20040730190047.GH21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
@ 2004-08-03 19:10 ` Andrew Barr
2004-08-03 23:23 ` Erik Tews
2004-08-04 1:18 ` Nathan Bryant
0 siblings, 2 replies; 54+ messages in thread
From: Andrew Barr @ 2004-08-03 19:10 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
My card came in the mail today...it works fine except for...(you guessed
it) S3 suspend with a framebuffer. The card never re-initializes (even
with acpi_sleep=s3_bios) and the monitor never powers back up. I can do
swsusp2, which is okay for now, but I guess my question at this point is
this: does anyone know what is keeping this card from working right with
a framebuffer over S3? More to the point, it is something that could be
fixed? Given how far the ACPI code has come in 2.6, I would certainly
hope something is possible.
Andrew
P.S. In case you're wondering, yes, I'm a bit of a perfectionist. ;)
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* Re: Radeon PM Support
2004-08-03 19:10 ` Andrew Barr
@ 2004-08-03 23:23 ` Erik Tews
2004-08-04 1:18 ` Nathan Bryant
1 sibling, 0 replies; 54+ messages in thread
From: Erik Tews @ 2004-08-03 23:23 UTC (permalink / raw)
To: Andrew Barr; +Cc: Acpi Devel
Am Di, den 03.08.2004 schrieb Andrew Barr um 21:10:
> My card came in the mail today...it works fine except for...(you guessed
> it) S3 suspend with a framebuffer. The card never re-initializes (even
> with acpi_sleep=s3_bios) and the monitor never powers back up. I can do
> swsusp2, which is okay for now, but I guess my question at this point is
> this: does anyone know what is keeping this card from working right with
> a framebuffer over S3? More to the point, it is something that could be
> fixed? Given how far the ACPI code has come in 2.6, I would certainly
> hope something is possible.
>
> Andrew
>
> P.S. In case you're wondering, yes, I'm a bit of a perfectionist. ;)
Well, I got a radeon 9600 too, and it never comes back too. I did not
try swsuspend or any special parameters. If you find a solution, please
tell me.
I heard that somebody has a t41p running with acpi, but I could't get my
system working with acpi here.
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* Re: Radeon PM Support
2004-08-03 19:10 ` Andrew Barr
2004-08-03 23:23 ` Erik Tews
@ 2004-08-04 1:18 ` Nathan Bryant
[not found] ` <41103952.2030707-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
1 sibling, 1 reply; 54+ messages in thread
From: Nathan Bryant @ 2004-08-04 1:18 UTC (permalink / raw)
To: Andrew Barr; +Cc: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Andrew Barr wrote:
>My card came in the mail today...it works fine except for...(you guessed
>it) S3 suspend with a framebuffer. The card never re-initializes (even
>with acpi_sleep=s3_bios) and the monitor never powers back up. I can do
>swsusp2, which is okay for now, but I guess my question at this point is
>this: does anyone know what is keeping this card from working right with
>a framebuffer over S3? More to the point, it is something that could be
>fixed? Given how far the ACPI code has come in 2.6, I would certainly
>hope something is possible.
>
>
The problem is in the graphics driver. Unfortunately graphics drivers
are a bit of a mess on linux: there are multiple drivers that all may
think they "own" the device. There are non-DRI X drivers that don't
incorporate any kernel functionality, DRI-based drivers that do include
kernel components, the text console driver (which knows nothing about
specific hardware), the framebuffer drivers... one or all of those
drivers needs to be taught how to resume the card, and if more than one
driver is running at once, they need to coordinate resume functionality
amongst themselves.
Good luck getting the drivers talking amongt one another if one of them
is not open source...
Also there are issues with AGPGART not knowing how to resume certain AGP
bus chipsets.
>P.S. In case you're wondering, yes, I'm a bit of a perfectionist. ;)
>
>
Sounds like we have a volunteer to clean up the whole mess :-)
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* Re: Radeon PM Support
[not found] ` <41103952.2030707-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
@ 2004-08-04 1:33 ` Erik Tews
[not found] ` <1091583216.2974.2.camel-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Erik Tews @ 2004-08-04 1:33 UTC (permalink / raw)
To: Nathan Bryant; +Cc: Andrew Barr, Acpi Devel
Am Mi, den 04.08.2004 schrieb Nathan Bryant um 3:18:
> The problem is in the graphics driver. Unfortunately graphics drivers
> are a bit of a mess on linux: there are multiple drivers that all may
> think they "own" the device. There are non-DRI X drivers that don't
> incorporate any kernel functionality, DRI-based drivers that do include
> kernel components, the text console driver (which knows nothing about
> specific hardware), the framebuffer drivers... one or all of those
> drivers needs to be taught how to resume the card, and if more than one
> driver is running at once, they need to coordinate resume functionality
> amongst themselves.
>
> Good luck getting the drivers talking amongt one another if one of them
> is not open source...
>
> Also there are issues with AGPGART not knowing how to resume certain AGP
> bus chipsets.
Well, if somebody would have a configuration, like add this
framebuffer-support, drop this dri-driver, then it works, it would be
enough for me.
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* Re: Radeon PM Support
[not found] ` <1091583216.2974.2.camel-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
@ 2004-08-04 3:40 ` Len Brown
2004-08-04 6:43 ` ole.rohne-vJEk5272eHo
0 siblings, 1 reply; 54+ messages in thread
From: Len Brown @ 2004-08-04 3:40 UTC (permalink / raw)
To: Erik Tews; +Cc: Nathan Bryant, Andrew Barr, Acpi Devel
Some folks have had good luck getting Radeon to resume
after applying this patch. I saw it fix a Dell 600m/Radeon.
http://lists.debian.org/debian-x/2004/03/msg03482.html
cheers,
-Len
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* Re: Radeon PM Support
2004-08-04 3:40 ` Len Brown
@ 2004-08-04 6:43 ` ole.rohne-vJEk5272eHo
[not found] ` <yzohdrjqu6p.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: ole.rohne-vJEk5272eHo @ 2004-08-04 6:43 UTC (permalink / raw)
To: Acpi Devel; +Cc: Erik Tews, Nathan Bryant, Andrew Barr, Len Brown
Len> Some folks have had good luck getting Radeon to resume
Len> after applying this patch. I saw it fix a Dell 600m/Radeon.
Len> http://lists.debian.org/debian-x/2004/03/msg03482.html
The same folks were even happier with a more recent patch that moves
the S3 resume POST where really belongs: into kernel space:
<http://article.gmane.org/gmane.linux.acpi.devel/8879>
Ole
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* Re: Radeon PM Support
[not found] ` <yzohdrjqu6p.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
@ 2004-08-04 7:17 ` Ow Mun Heng
2004-08-04 7:17 ` wwp
2004-08-04 14:52 ` Len Brown
2 siblings, 0 replies; 54+ messages in thread
From: Ow Mun Heng @ 2004-08-04 7:17 UTC (permalink / raw)
To: Acpi Devel
On Tue, 2004-08-03 at 23:43, ole.rohne-vJEk5272eHo@public.gmane.org wrote:
> Len> Some folks have had good luck getting Radeon to resume
> Len> after applying this patch. I saw it fix a Dell 600m/Radeon.
>
> Len> http://lists.debian.org/debian-x/2004/03/msg03482.html
>
> The same folks were even happier with a more recent patch that moves
> the S3 resume POST where really belongs: into kernel space:
>
> <http://article.gmane.org/gmane.linux.acpi.devel/8879>
I've got to try this out. I have a D600 running on FC2.
S4 works great.. S3.. not so.
When I have time...
Sigh..
interesting info though.. Thanks
--
Ow Mun Heng
Fedora GNU/Linux Core 2 on D600 1.4Ghz CPU kernel
2.6.7-2.jul1-interactive
Neuromancer 00:16:43 up 11:31, 5 users, load average: 0.69, 0.66, 0.61
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* Re: Radeon PM Support
[not found] ` <yzohdrjqu6p.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-04 7:17 ` Ow Mun Heng
@ 2004-08-04 7:17 ` wwp
2004-08-04 14:52 ` Len Brown
2 siblings, 0 replies; 54+ messages in thread
From: wwp @ 2004-08-04 7:17 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Hello ole.rohne-vJEk5272eHo@public.gmane.org,
On 04 Aug 2004 08:43:58 +0200 ole.rohne-vJEk5272eHo@public.gmane.org wrote:
> Len> Some folks have had good luck getting Radeon to resume
> Len> after applying this patch. I saw it fix a Dell 600m/Radeon.
>
> Len> http://lists.debian.org/debian-x/2004/03/msg03482.html
>
> The same folks were even happier with a more recent patch that moves
> the S3 resume POST where really belongs: into kernel space:
>
> <http://article.gmane.org/gmane.linux.acpi.devel/8879>
Is there a possible equivalent to 2.4 kernels (if only it is relevant)?
Regards,
--
wwp
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* Re: Radeon PM Support
[not found] ` <yzohdrjqu6p.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-04 7:17 ` Ow Mun Heng
2004-08-04 7:17 ` wwp
@ 2004-08-04 14:52 ` Len Brown
2004-08-04 17:44 ` count0-tC47gz4GrgtWk0Htik3J/w
2004-08-06 6:13 ` ole.rohne-vJEk5272eHo
2 siblings, 2 replies; 54+ messages in thread
From: Len Brown @ 2004-08-04 14:52 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo; +Cc: Acpi Devel, Erik Tews, Nathan Bryant, Andrew Barr
On Wed, 2004-08-04 at 02:43, ole.rohne-vJEk5272eHo@public.gmane.org wrote:
> Len> Some folks have had good luck getting Radeon to resume
> Len> after applying this patch. I saw it fix a Dell 600m/Radeon.
>
> Len> http://lists.debian.org/debian-x/2004/03/msg03482.html
>
> The same folks were even happier with a more recent patch that moves
> the S3 resume POST where really belongs: into kernel space:
>
> <http://article.gmane.org/gmane.linux.acpi.devel/8879>
Thanks Ole, for pointing that out.
I too would prefer a kernel-based solution that
applies to all video adapters. I would
like a solution that applies to x86_64
in addition to i386.
I saw the note about this patch fixing the dell 600m
with the Radeon 9000. I haven't yet seen reports of it
fixing other system's video on S3 resume, including
the Radeon 7000 that is the subject of this thread.
Can you summarize the feedback you've got so far?
Can you re-post the cleaned up patch?
Maybe good to go to lkml with it for broader review
and feedback.
thanks,
-Len
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* Re: Radeon PM Support
2004-08-04 14:52 ` Len Brown
@ 2004-08-04 17:44 ` count0-tC47gz4GrgtWk0Htik3J/w
[not found] ` <52654.199.172.169.15.1091641493.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
2004-08-06 6:13 ` ole.rohne-vJEk5272eHo
1 sibling, 1 reply; 54+ messages in thread
From: count0-tC47gz4GrgtWk0Htik3J/w @ 2004-08-04 17:44 UTC (permalink / raw)
To: len.brown-ral2JQCrhuEAvxtiuMwx3w
Cc: ole.rohne-vJEk5272eHo,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
erik-KVSZC2aA8+zw/snApU8qRLNAH6kLmebB,
nbryant-p32f3XyCuykqcZcGjlUOXw, barr.156-ZbGKxL/pcrQ
This S3 resume POST patch has to go into the official ACPI/kernel
source, just has to. POST'ing the video adapter on resume is
absolutely fundamental. That some older non-Radeon cards can
do without and we've gone this long without it is just amazing
coincidence. This should go in right away, anything is better
than nothing. -Huw
> On Wed, 2004-08-04 at 02:43, ole.rohne-vJEk5272eHo@public.gmane.org wrote:
>> Len> Some folks have had good luck getting Radeon to resume
>> Len> after applying this patch. I saw it fix a Dell 600m/Radeon.
>>
>> Len> http://lists.debian.org/debian-x/2004/03/msg03482.html
>>
>> The same folks were even happier with a more recent patch that moves
>> the S3 resume POST where really belongs: into kernel space:
>>
>> <http://article.gmane.org/gmane.linux.acpi.devel/8879>
>
> Thanks Ole, for pointing that out.
> I too would prefer a kernel-based solution that
> applies to all video adapters. I would
> like a solution that applies to x86_64
> in addition to i386.
>
> I saw the note about this patch fixing the dell 600m
> with the Radeon 9000. I haven't yet seen reports of it
> fixing other system's video on S3 resume, including
> the Radeon 7000 that is the subject of this thread.
> Can you summarize the feedback you've got so far?
>
> Can you re-post the cleaned up patch?
> Maybe good to go to lkml with it for broader review
> and feedback.
>
> thanks,
> -Len
>
>
>
>
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <52654.199.172.169.15.1091641493.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
@ 2004-08-04 17:48 ` Nathan Bryant
[not found] ` <4111217B.8000900-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
2004-08-04 19:00 ` Stefan Dösinger
1 sibling, 1 reply; 54+ messages in thread
From: Nathan Bryant @ 2004-08-04 17:48 UTC (permalink / raw)
To: count0-tC47gz4GrgtWk0Htik3J/w
Cc: len.brown-ral2JQCrhuEAvxtiuMwx3w, ole.rohne-vJEk5272eHo,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
erik-KVSZC2aA8+zw/snApU8qRLNAH6kLmebB, barr.156-ZbGKxL/pcrQ
count0-tC47gz4GrgtWk0Htik3J/w@public.gmane.org wrote:
> This S3 resume POST patch has to go into the official ACPI/kernel
> source, just has to. POST'ing the video adapter on resume is
> absolutely fundamental. That some older non-Radeon cards can
> do without and we've gone this long without it is just amazing
> coincidence. This should go in right away, anything is better
> than nothing. -Huw
Huh? acpi_sleep=s3_bios is in the mainline.
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <4111217B.8000900-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
@ 2004-08-04 18:23 ` count0-tC47gz4GrgtWk0Htik3J/w
[not found] ` <62466.199.172.169.15.1091643791.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: count0-tC47gz4GrgtWk0Htik3J/w @ 2004-08-04 18:23 UTC (permalink / raw)
To: nbryant-p32f3XyCuykqcZcGjlUOXw
Cc: len.brown-ral2JQCrhuEAvxtiuMwx3w, ole.rohne-vJEk5272eHo,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
erik-KVSZC2aA8+zw/snApU8qRLNAH6kLmebB, barr.156-ZbGKxL/pcrQ
> count0-tC47gz4GrgtWk0Htik3J/w@public.gmane.org wrote:
>> This S3 resume POST patch has to go into the official ACPI/kernel
>> source, just has to. POST'ing the video adapter on resume is
>> absolutely fundamental. That some older non-Radeon cards can
>> do without and we've gone this long without it is just amazing
>> coincidence. This should go in right away, anything is better
>> than nothing. -Huw
>
> Huh? acpi_sleep=s3_bios is in the mainline.
It doesn't work, and it never has except in serendipitous
circumstances. It happens at the wrong time, with interrupts
in completely the wrong state. If it ever worked for anyone,
it's a miracle that should not be regarded as a reason to
perpetuate it. Let's get rid of it and replace it with the
right solution - this more recent patch. -Huw
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <62466.199.172.169.15.1091643791.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
@ 2004-08-04 18:35 ` Eric Valette
0 siblings, 0 replies; 54+ messages in thread
From: Eric Valette @ 2004-08-04 18:35 UTC (permalink / raw)
To: count0-tC47gz4GrgtWk0Htik3J/w; +Cc: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
count0-tC47gz4GrgtWk0Htik3J/w@public.gmane.org wrote:
>>count0-tC47gz4GrgtWk0Htik3J/w@public.gmane.org wrote:
>>
>>>This S3 resume POST patch has to go into the official ACPI/kernel
>>>source, just has to. POST'ing the video adapter on resume is
>>>absolutely fundamental. That some older non-Radeon cards can
>>>do without and we've gone this long without it is just amazing
>>>coincidence. This should go in right away, anything is better
>>>than nothing. -Huw
>>
>>Huh? acpi_sleep=s3_bios is in the mainline.
>
>
> It doesn't work, and it never has except in serendipitous
> circumstances. It happens at the wrong time, with interrupts
> in completely the wrong state. If it ever worked for anyone,
> it's a miracle that should not be regarded as a reason to
> perpetuate it. Let's get rid of it and replace it with the
> right solution - this more recent patch. -Huw
At least is works for me (radeon 7500, Ausus L3800C).
Note that I would be glad not to rely on the BIOS but I think your
wording is a little bit strong...
-- eric
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <52654.199.172.169.15.1091641493.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
2004-08-04 17:48 ` Nathan Bryant
@ 2004-08-04 19:00 ` Stefan Dösinger
[not found] ` <200408042100.24705.stefandoesinger-RbZlAiThDcE@public.gmane.org>
1 sibling, 1 reply; 54+ messages in thread
From: Stefan Dösinger @ 2004-08-04 19:00 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: count0-tC47gz4GrgtWk0Htik3J/w, len.brown-ral2JQCrhuEAvxtiuMwx3w,
ole.rohne-vJEk5272eHo, erik-KVSZC2aA8+zw/snApU8qRLNAH6kLmebB,
nbryant-p32f3XyCuykqcZcGjlUOXw, barr.156-ZbGKxL/pcrQ
Am Mittwoch, 4. August 2004 19:44 schrieb count0-tC47gz4GrgtWk0Htik3J/w@public.gmane.org:
> This S3 resume POST patch has to go into the official ACPI/kernel
> source, just has to. POST'ing the video adapter on resume is
> absolutely fundamental. That some older non-Radeon cards can
> do without and we've gone this long without it is just amazing
> coincidence. This should go in right away, anything is better
> than nothing. -Huw
I think this patch only works for radeon cards, and not in all circumstances.
It doesn't work for me(ATI Technologies Inc Radeon R250 Lf [Radeon Mobility
9000] (rev 01)). Strangely, user mode based VGA rom post works.
I am allready trying to debug this with Ole, but it seems that he's on
holyday. Any ideas?
There is some resume code in drivers/video/aty/radeon_pm.c written by ATI, but
it's only compiled on PowerMac and is only tested for <=R200 and S2.
I tried to activate it(remove arch and model checking), but it only made my
display flash a few times. Perhaps we should ask ATI for help.
Stefan
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <200408042100.24705.stefandoesinger-RbZlAiThDcE@public.gmane.org>
@ 2004-08-05 7:33 ` ole.rohne-vJEk5272eHo
[not found] ` <yzo7jse5999.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: ole.rohne-vJEk5272eHo @ 2004-08-05 7:33 UTC (permalink / raw)
To: stefandoesinger-RbZlAiThDcE
Cc: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
count0-tC47gz4GrgtWk0Htik3J/w, len.brown-ral2JQCrhuEAvxtiuMwx3w,
erik-KVSZC2aA8+zw/snApU8qRLNAH6kLmebB,
nbryant-p32f3XyCuykqcZcGjlUOXw, barr.156-ZbGKxL/pcrQ
Stefan> I think this patch only works for radeon cards,
I'd rather say it is perhaps only reported to be needed for Radeon
cards, VGA POST'ing as such is of course not chipset specific.
I'd maintain that ACPI makes no promise that the graphics chipset is
reinitialized on S3 resume. So if an adapter "just works", it is
either because the device hasn't been completely powered down (Dn, n<3?)
or because the system BIOS graciously takes care of the POSTing
Stefan> and not in all circumstances.
Which is disappointing:-(
Stefan> I am allready trying to debug this with Ole, but it seems that
Stefan> he's on holyday.
No, I'm just attending my daytime job;-) Sorry if I dropped out on one
of your mails.
Stefan> Any ideas?
Yes, two:
1. Try supplying the bus number with the devfn argument:
acpi_vgapost (pdev->bus->number << 8 | pdev->devfn);
2. Check that the VGA BIOS is really there before calling it. IIRC, the
signature at 0xc000:0 should be 0xaa55
Stefan> There is some resume code in drivers/video/aty/radeon_pm.c
Stefan> written by ATI, but it's only compiled on PowerMac and is only
Stefan> tested for <=R200 and S2.
^^-- Do you mean D2?
I've played with earlier versions of this code in radeonfb. In my
understanding D2 is low power still retaining some state, so the
PowerMac code is not a complete cold boot.
Stefan> Perhaps we should ask ATI for help.
I guess it could be tried; someone pessimistically predicted the
answer as "use the BIOS".
Ole
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <yzo7jse5999.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
@ 2004-08-05 12:27 ` Tomasz Ciolek
2004-08-05 12:53 ` Stefan Dösinger
1 sibling, 0 replies; 54+ messages in thread
From: Tomasz Ciolek @ 2004-08-05 12:27 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo
Cc: stefandoesinger-RbZlAiThDcE,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
count0-tC47gz4GrgtWk0Htik3J/w, len.brown-ral2JQCrhuEAvxtiuMwx3w,
erik-KVSZC2aA8+zw/snApU8qRLNAH6kLmebB,
nbryant-p32f3XyCuykqcZcGjlUOXw, barr.156-ZbGKxL/pcrQ
[-- Attachment #1: Type: text/plain, Size: 906 bytes --]
On Thu, Aug 05, 2004 at 09:33:54AM +0200, ole.rohne-vJEk5272eHo@public.gmane.org wrote:
>
> I guess it could be tried; someone pessimistically predicted the
> answer as "use the BIOS".
>
> Ole
Ben Herrenschmidt the linux PPC maintainer looked at it at one point. It
appears that for some of the ATI Vide cards in laptops (Fujitsu P2120 is
one), the Video Bios is co-lclated with main system bios... which makes it
hard to post gracefuly.
Tomasz
--
Tomasz M. Ciolek
*******************************************************************************
tmc at dreamcraft dot com dot au
*******************************************************************************
GPG Key ID: 0x41C4C2F0
GPG Key Fingerprint: 3883 B308 8256 2246 D3ED A1FF 3A1D 0EAD 41C4 C2F0
Key available on www.pgp.net
*******************************************************************************
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <yzo7jse5999.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-05 12:27 ` Tomasz Ciolek
@ 2004-08-05 12:53 ` Stefan Dösinger
[not found] ` <200408051453.55710.stefandoesinger-RbZlAiThDcE@public.gmane.org>
1 sibling, 1 reply; 54+ messages in thread
From: Stefan Dösinger @ 2004-08-05 12:53 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f; +Cc: ole.rohne-vJEk5272eHo
Am Donnerstag, 5. August 2004 09:33 schrieb ole.rohne-vJEk5272eHo@public.gmane.org:
> Stefan> I think this patch only works for radeon cards,
>
> I'd rather say it is perhaps only reported to be needed for Radeon
> cards, VGA POST'ing as such is of course not chipset specific.
>
> I'd maintain that ACPI makes no promise that the graphics chipset is
> reinitialized on S3 resume. So if an adapter "just works", it is
> either because the device hasn't been completely powered down (Dn, n<3?)
> or because the system BIOS graciously takes care of the POSTing
Intel's new graphics chipset probably. Owners of Acer Travelmate 60X told me
that the video doesn't come back. But in the these case the whole system
locked up on resume, so we can't tell if the video resume works.
I don't know much about this ROM post call. You mean all cards understand it?
>
> Stefan> and not in all circumstances.
>
> Which is disappointing:-(
I wrote a small "driver" for my radeon card which calls acpi_vgapost in the
pci probe function. The screen went black and the system locked up. Is your
code supposed to work without prior suspending?
> No, I'm just attending my daytime job;-) Sorry if I dropped out on one
> of your mails.
Not of a problem
>
> Stefan> Any ideas?
>
> Yes, two:
>
> 1. Try supplying the bus number with the devfn argument:
> acpi_vgapost (pdev->bus->number << 8 | pdev->devfn);
Tried this, no change, system doesn't resume.
> 2. Check that the VGA BIOS is really there before calling it. IIRC, the
> signature at 0xc000:0 should be 0xaa55
How can I do this?
cmp c000:0, 0aa55h
jne skip_rompost
call_bios
skip_rompost:
Something like this? Or can I do this in radeonfb with C code?
>
> Stefan> There is some resume code in drivers/video/aty/radeon_pm.c
> Stefan> written by ATI, but it's only compiled on PowerMac and is only
> Stefan> tested for <=R200 and S2.
> ^^-- Do you mean D2?
D2 of course...
>
> I've played with earlier versions of this code in radeonfb. In my
> understanding D2 is low power still retaining some state, so the
> PowerMac code is not a complete cold boot.
>
> Stefan> Perhaps we should ask ATI for help.
>
> I guess it could be tried; someone pessimistically predicted the
> answer as "use the BIOS".
I think the the Xfree and DRI guys have the specs(but under NDA). Perhaps
someone is willing to check if there's some way to bring the card back and fix
radeon_pm.c
Stefan
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <200408051453.55710.stefandoesinger-RbZlAiThDcE@public.gmane.org>
@ 2004-08-05 17:14 ` Alexander Bruder
[not found] ` <200408051914.39445.anib-La3J9u0raUk@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Alexander Bruder @ 2004-08-05 17:14 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
Hi,
> Intel's new graphics chipset probably. Owners of Acer Travelmate 60X told
> me that the video doesn't come back. But in the these case the whole system
> locked up on resume, so we can't tell if the video resume works.
it also happends for the 80x series (in my case 801Lcib) with ATI Technologies
Inc Radeon R250 Lf [Radeon Mobility 9000] using the framebuffer.
"echo 3 > /proc/acpi/sleep" and "echo 4 > /proc/acpi/sleep" doesn't work
because video doesn't come back as described by Stefan. The only reaction is
the fan which runs like hell and doesn't stop. Same thing with pmdisk and
suspend to disk ("echo -n disk > /sys/power/state"). All tested with recent
kernels 2.6.7-2.6.8-rc3 .
But with swsusp2 as the suspend to disk system ("echo
> /proc/swsusp/activate" ) on a 2.6.7 kernel the video card recovers!?!
I don't know much about the whole thing and why swsusp2 can (help) recover(s)
the video card but perhaps it may help you.
Alexander
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^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: Radeon PM Support
@ 2004-08-05 17:52 Pallipadi, Venkatesh
[not found] ` <88056F38E9E48644A0F562A38C64FB600289AE7C-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Pallipadi, Venkatesh @ 2004-08-05 17:52 UTC (permalink / raw)
To: anib-La3J9u0raUk, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
[-- Attachment #1: Type: text/plain, Size: 2350 bytes --]
Does this addon patch (over the Ole's original patch) help?
This works with Radeon 9000M and frame buffer for me. This
should also help any other graphics drivers which doesn't
implement their own suspend resume functions.
I just hope that this video reposting won't break any of the
already working systems :).
Thanks,
Venki
>-----Original Message-----
>From: acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
>[mailto:acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org] On Behalf Of
>Alexander Bruder
>Sent: Thursday, August 05, 2004 10:15 AM
>To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org; stefandoesinger-RbZlAiThDcE@public.gmane.org
>Subject: Re: [ACPI] Radeon PM Support
>
>Hi,
>
>> Intel's new graphics chipset probably. Owners of Acer
>Travelmate 60X told
>> me that the video doesn't come back. But in the these case
>the whole system
>> locked up on resume, so we can't tell if the video resume works.
>
>it also happends for the 80x series (in my case 801Lcib) with
>ATI Technologies
>Inc Radeon R250 Lf [Radeon Mobility 9000] using the framebuffer.
>"echo 3 > /proc/acpi/sleep" and "echo 4 > /proc/acpi/sleep"
>doesn't work
>because video doesn't come back as described by Stefan. The
>only reaction is
>the fan which runs like hell and doesn't stop. Same thing with
>pmdisk and
>suspend to disk ("echo -n disk > /sys/power/state"). All
>tested with recent
>kernels 2.6.7-2.6.8-rc3 .
>But with swsusp2 as the suspend to disk system ("echo
>> /proc/swsusp/activate" ) on a 2.6.7 kernel the video card
>recovers!?!
>I don't know much about the whole thing and why swsusp2 can
>(help) recover(s)
>the video card but perhaps it may help you.
>
>
>Alexander
>
>
>-------------------------------------------------------
>This SF.Net email is sponsored by OSTG. Have you noticed the changes on
>Linux.com, ITManagersJournal and NewsForge in the past few weeks? Now,
>one more big change to announce. We are now OSTG- Open Source
>Technology
>Group. Come see the changes on the new OSTG site. www.ostg.com
>_______________________________________________
>Acpi-devel mailing list
>Acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
>https://lists.sourceforge.net/lists/listinfo/acpi-devel
>
[-- Attachment #2: videoresume-addon.patch --]
[-- Type: application/octet-stream, Size: 544 bytes --]
--- linux-2.6.7-s3//drivers/pci/pci-driver.c.org 2004-07-22 18:59:40.446392744 -0700
+++ linux-2.6.7-s3//drivers/pci/pci-driver.c 2004-07-22 18:59:52.473564336 -0700
@@ -334,8 +334,12 @@ static int pci_device_resume(struct devi
pci_set_power_state(pci_dev, 0);
if (drv && drv->resume)
drv->resume(pci_dev);
- else
+ else {
pci_default_resume(pci_dev);
+ /* If video device do a video repost */
+ if ((pci_dev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
+ acpi_vgapost(pci_dev->devfn);
+ }
return 0;
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <200408051914.39445.anib-La3J9u0raUk@public.gmane.org>
@ 2004-08-05 19:53 ` Stefan Dösinger
[not found] ` <200408052153.25467.stefandoesinger-RbZlAiThDcE@public.gmane.org>
2004-08-06 20:03 ` Ow Mun Heng
1 sibling, 1 reply; 54+ messages in thread
From: Stefan Dösinger @ 2004-08-05 19:53 UTC (permalink / raw)
To: anib-La3J9u0raUk; +Cc: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
[-- Attachment #1: Type: text/plain, Size: 1114 bytes --]
Am Donnerstag, 5. August 2004 19:14 schrieb Alexander Bruder:
> it also happends for the 80x series (in my case 801Lcib) with ATI
> Technologies Inc Radeon R250 Lf [Radeon Mobility 9000] using the
> framebuffer.
I use an Acer TM 803.....
Suspend to RAM works with user mode VGA ROM post.
Just a short HOWTO(based on kernel 2.6.8-rc2 + recent acpi patch from
acpi.sf.net):
*Apply the resume-finish-split patch to the kernel.
*Use the attached dsdt(see acpi.sf.net how to do this)
*the boot-radeon.c program can ROM-post the radeon card(compile with gcc
boot-radeon.c -o boot-radeon -llrmi) You need the lrmi libs+headers. Call it
after resuming from S3. You have to call it from console. If you use X, you
can do this:
chvt 1
boot-radeon
chvt 7
Before going to S3 you'll have to unload ehci-hcd. All other drivers may
remain loaded.
The things that do not work properly:
*VGA resume with radeonfb, the most annoying problem
*sending ehci-hcd to suspend fails. uhci works
*restoring irq routing on resume. That's what the modified dsdt is for. It
forces the wlan card to use IRQ10 instead of IRQ11.
Stefan
[-- Attachment #2: resume-finish-split.patch --]
[-- Type: text/x-diff, Size: 1774 bytes --]
--- linux-2.6.8-rc2/include/linux/pm.h 2004-08-04 20:36:48.044455680 +0200
+++ include/linux/pm.h 2004-08-04 19:50:07.000000000 +0200
@@ -214,6 +214,7 @@
u32 pm_disk_mode;
int (*prepare)(u32 state);
int (*enter)(u32 state);
+ int (*leave)(u32 state);
int (*finish)(u32 state);
};
--- linux-2.6.8-rc2/kernel/power/main.c 2004-08-04 20:36:17.755060368 +0200
+++ kernel/power/main.c 2004-08-04 19:52:26.000000000 +0200
@@ -108,6 +108,8 @@
static void suspend_finish(u32 state)
{
+ if (pm_ops && pm_ops->leave)
+ pm_ops->leave(state);
device_resume();
if (pm_ops && pm_ops->finish)
pm_ops->finish(state);
--- linux-2.6.8-rc2/drivers/acpi/sleep/main.c 2004-08-04 20:29:23.863981376 +0200
+++ drivers/acpi/sleep/main.c 2004-08-04 20:33:41.348837728 +0200
@@ -127,7 +127,23 @@
return ACPI_SUCCESS(status) ? 0 : -EFAULT;
}
+/**
+ * acpi_pm_leave - Make system ready to resume devices.
+ * @pm_state: State we're coming out of.
+ *
+ * This is called after we wake back up and before device
+ * resume methods are called.
+ */
+
+static int acpi_pm_leave(u32 pm_state)
+{
+ u32 acpi_state = acpi_suspend_states[pm_state];
+ acpi_leave_sleep_state(acpi_state);
+ acpi_disable_wakeup_device(acpi_state);
+
+ return 0;
+}
/**
* acpi_pm_finish - Finish up suspend sequence.
* @pm_state: State we're coming out of.
@@ -140,9 +156,6 @@
{
u32 acpi_state = acpi_suspend_states[pm_state];
- acpi_leave_sleep_state(acpi_state);
- acpi_disable_wakeup_device(acpi_state);
-
/* reset firmware waking vector */
acpi_set_firmware_waking_vector((acpi_physical_address) 0);
@@ -170,6 +183,7 @@
static struct pm_ops acpi_pm_ops = {
.prepare = acpi_pm_prepare,
.enter = acpi_pm_enter,
+ .leave = acpi_pm_leave,
.finish = acpi_pm_finish,
};
[-- Attachment #3: ACER-TravelMate_800-4a12-custom.asl --]
[-- Type: text/x-csrc, Size: 203511 bytes --]
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20040527
*
* Disassembly of dsdt.dat, Wed Jul 7 22:53:26 2004
*/
DefinitionBlock ("DSDT.aml", "DSDT", 1, "ACER ", "Cardinal", 537003824)
{
OperationRegion (DBG, SystemIO, 0x80, 0x01)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DEBG, 8
}
Scope (_PR)
{
Processor (CPU0, 0x00, 0x00001010, 0x06)
{
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (SystemIO, 0x08, 0x00, 0x00000000000000B2)
},
ResourceTemplate ()
{
Register (SystemIO, 0x08, 0x00, 0x00000000000000B3)
}
})
Name (_PSS, Package (0x05)
{
Package (0x06)
{
0x0640,
0x5DC0,
0x0A,
0x0A,
0x89,
0x00
},
Package (0x06)
{
0x0578,
0x4E20,
0x0A,
0x0A,
0x8A,
0x01
},
Package (0x06)
{
0x04B0,
0x4650,
0x0A,
0x0A,
0x8B,
0x02
},
Package (0x06)
{
0x0320,
0x3E80,
0x0A,
0x0A,
0x8C,
0x03
},
Package (0x06)
{
0x0258,
0x2EE0,
0x0A,
0x0A,
0x8D,
0x04
}
})
Method (_PPC, 0, NotSerialized)
{
Return (0x00)
}
}
}
Scope (_SI)
{
Method (_MSG, 1, NotSerialized)
{
If (Arg0)
{
Store (One, \_SB.PCI0.LPC0.BL27)
}
Else
{
Store (Zero, \_SB.PCI0.LPC0.BL27)
}
}
}
Name (\_S0, Package (0x02)
{
0x00,
0x00
})
Name (\_S3, Package (0x02)
{
0x05,
0x05
})
Name (\_S4, Package (0x02)
{
0x06,
0x06
})
Name (\_S5, Package (0x02)
{
0x07,
0x07
})
Method (_PTS, 1, NotSerialized)
{
Store (Arg0, \_SB.STAT)
Store (">>>> _PTS ------------", Debug)
Store (Arg0, Debug)
Store (Arg0, \_SB.SLEE)
Store (0x84, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
If (Or (LEqual (Arg0, 0x03), LEqual (Arg0, 0x04)))
{
Store (0x01, \_SB.PCI0.LPC0.EC0.APWR)
}
If (LEqual (Arg0, 0x03))
{
Store (0x80, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
If (LEqual (Arg0, 0x04))
{
Store (0x01, \_SB.S4WP)
Store (0x82, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
Store (One, \_SB.PCI0.LPC0.EC0.PFLG)
Store (One, \_SB.PCI0.LPC0.EC0.S4LD)
}
If (LEqual (SizeOf (\_OS), 0x27))
{
Notify (\_SB.BAT1, 0x80)
Notify (\_SB.BAT2, 0x80)
Notify (\_SB.ACAD, 0x00)
}
If (LEqual (Arg0, 0x05))
{
Store (One, \_SB.PCI0.LPC0.EC0.S5LW)
}
}
Method (_WAK, 1, NotSerialized)
{
Store (">>>> _WAK ------------", Debug)
Store (Arg0, Debug)
Store (Arg0, \_SB.STAT)
If (LEqual (Arg0, 0x03))
{
Store (0x81, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
If (LEqual (Arg0, 0x04))
{
Store (0x01, \_SB.OKEC)
Notify (\_SB.SLPB, 0x02)
}
If (LEqual (SizeOf (\_OS), 0x14))
{
Store (\_SB.PCI0.LPC0.RBID, Local0)
Store (\_SB.PCI0.IDE0.BAYR, Local1)
Store (Local0, \_SB.PCI0.IDE0.BAYR)
If (LNot (LEqual (Local0, Local1)))
{
If (Or (LEqual (Local1, 0x01), LEqual (Local1, 0x02)))
{
If (And (LEqual (\_SB.PCI0.MYOS, 0x03), LEqual (Local0, 0x03)))
{
Notify (\_SB.PCI0.IDE0.SECN.BAY1, 0x03)
}
Else
{
Notify (\_SB.PCI0.IDE0.SECN.BAY1, 0x01)
}
}
}
If (Or (LEqual (Local0, 0x01), LEqual (Local0, 0x02)))
{
Notify (\_SB.PCI0.IDE0.SECN.BAY1, 0x00)
}
}
If (LEqual (SizeOf (\_OS), 0x27))
{
Notify (\_SB.BAT1, 0x80)
Notify (\_SB.BAT2, 0x80)
Notify (\_SB.ACAD, 0x00)
}
Store (\_SB.PCI0.LPC0.EC0.ACDF, \_SB.ACST)
If (LEqual (SizeOf (\_OS), 0x11))
{
Notify (\_SB.SLPB, 0x02)
}
Store (0x00, \_SB.SLEE)
}
Scope (_GPE)
{
Method (_L05, 0, NotSerialized)
{
Notify (\_SB.PCI0.MDM0, 0x02)
}
Method (_L0B, 0, NotSerialized)
{
Notify (\_SB.PCI0.HUB, 0x00)
If (Or (LEqual (\_SB.PCI0.MYOS, 0x01), LEqual (\_SB.PCI0.MYOS, 0x03)))
{
Notify (\_SB.SLPB, 0x02)
}
}
Method (_L03, 0, NotSerialized)
{
Notify (\_SB.PCI0.USB1, 0x02)
}
Method (_L04, 0, NotSerialized)
{
Notify (\_SB.PCI0.USB2, 0x02)
}
Method (_L0C, 0, NotSerialized)
{
Notify (\_SB.PCI0.USB3, 0x02)
}
Method (_E18, 0, NotSerialized)
{
Sleep (0x01)
}
}
Scope (_SB)
{
Name (STAT, 0x00)
Name (D1ST, 0x00)
Name (D1SJ, 0x01)
Device (PCI0)
{
Name (MYOS, 0x02)
Method (_INI, 0, NotSerialized)
{
Store (0x01, \_SB.D1SJ)
Store (0x02, MYOS)
If (LEqual (SizeOf (\_OS), 0x14))
{
Store (0x01, MYOS)
Store (0x01, \_SB.W2KF)
If (CondRefOf (_OSI, Local0))
{
If (\_OSI ("Windows 2001"))
{
Store (0x03, MYOS)
Store (0x03, \_SB.W2KF)
}
}
}
Else
{
If (LEqual (SizeOf (\_OS), 0x11))
{
Store (0x00, MYOS)
Store (0x00, \_SB.W2KF)
}
Else
{
If (LEqual (SizeOf (\_OS), 0x27))
{
Store (0x02, MYOS)
Store (0x02, \_SB.W2KF)
}
}
}
}
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_BBN, 0x00)
OperationRegion (HBUS, PCI_Config, 0x40, 0xC0)
Field (HBUS, DWordAcc, NoLock, Preserve)
{
Offset (0x20),
DRB0, 8,
DRB1, 8,
DRB2, 8,
DRB3, 8,
Offset (0x50),
, 4,
PM0H, 2,
Offset (0x51),
PM1L, 2,
, 2,
PM1H, 2,
Offset (0x52),
PM2L, 2,
, 2,
PM2H, 2,
Offset (0x53),
PM3L, 2,
, 2,
PM3H, 2,
Offset (0x54),
PM4L, 2,
, 2,
PM4H, 2,
Offset (0x55),
PM5L, 2,
, 2,
PM5H, 2,
Offset (0x56),
PM6L, 2,
, 2,
PM6H, 2,
Offset (0x57),
FDHC, 8
}
Name (BUF0, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000,
0x0000,
0x00FF,
0x0000,
0x0100, 0x00)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000,
0x00000000,
0x00000CF7,
0x00000000,
0x00000CF8, 0x00)
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000,
0x00000D00,
0x0000FFFF,
0x00000000,
0x0000F300, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000A0000,
0x000BFFFF,
0x00000000,
0x00020000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000C0000,
0x000C3FFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000C4000,
0x000C7FFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000C8000,
0x000CBFFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000CC000,
0x000CFFFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000D0000,
0x000D3FFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000D4000,
0x000D7FFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000D8000,
0x000DBFFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000DC000,
0x000DFFFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000E0000,
0x000E3FFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000E4000,
0x000E7FFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000E8000,
0x000EBFFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000EC000,
0x000EFFFF,
0x00000000,
0x00004000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x000F0000,
0x000FFFFF,
0x00000000,
0x00010000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x00000000,
0xFEBFFFFF,
0x00000000,
0x00000000, 0x00)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00)
})
Method (_CRS, 0, Serialized)
{
If (PM1L)
{
CreateDWordField (BUF0, 0x80, C0LN)
Store (Zero, C0LN)
}
If (LEqual (PM1L, 0x01))
{
CreateBitField (BUF0, 0x0378, C0RW)
Store (Zero, C0RW)
}
If (PM1H)
{
CreateDWordField (BUF0, 0x9B, C4LN)
Store (Zero, C4LN)
}
If (LEqual (PM1H, 0x01))
{
CreateBitField (BUF0, 0x0450, C4RW)
Store (Zero, C4RW)
}
If (PM2L)
{
CreateDWordField (BUF0, 0xB6, C8LN)
Store (Zero, C8LN)
}
If (LEqual (PM2L, 0x01))
{
CreateBitField (BUF0, 0x0528, C8RW)
Store (Zero, C8RW)
}
If (PM2H)
{
CreateDWordField (BUF0, 0xD1, CCLN)
Store (Zero, CCLN)
}
If (LEqual (PM2H, 0x01))
{
CreateBitField (BUF0, 0x0600, CCRW)
Store (Zero, CCRW)
}
If (PM3L)
{
CreateDWordField (BUF0, 0xEC, D0LN)
Store (Zero, D0LN)
}
If (LEqual (PM3L, 0x01))
{
CreateBitField (BUF0, 0x06D8, D0RW)
Store (Zero, D0RW)
}
If (PM3H)
{
CreateDWordField (BUF0, 0x0107, D4LN)
Store (Zero, D4LN)
}
If (LEqual (PM3H, 0x01))
{
CreateBitField (BUF0, 0x07B0, D4RW)
Store (Zero, D4RW)
}
If (PM4L)
{
CreateDWordField (BUF0, 0x0122, D8LN)
Store (Zero, D8LN)
}
If (LEqual (PM4L, 0x01))
{
CreateBitField (BUF0, 0x0888, D8RW)
Store (Zero, D8RW)
}
If (PM4H)
{
CreateDWordField (BUF0, 0x013D, DCLN)
Store (Zero, DCLN)
}
If (LEqual (PM4H, 0x01))
{
CreateBitField (BUF0, 0x0960, DCRW)
Store (Zero, DCRW)
}
If (PM5L)
{
CreateDWordField (BUF0, 0x0158, E0LN)
Store (Zero, E0LN)
}
If (LEqual (PM5L, 0x01))
{
CreateBitField (BUF0, 0x0A38, E0RW)
Store (Zero, E0RW)
}
If (PM5H)
{
CreateDWordField (BUF0, 0x0173, E4LN)
Store (Zero, E4LN)
}
If (LEqual (PM5H, 0x01))
{
CreateBitField (BUF0, 0x0B10, E4RW)
Store (Zero, E4RW)
}
If (PM6L)
{
CreateDWordField (BUF0, 0x018E, E8LN)
Store (Zero, E8LN)
}
If (LEqual (PM6L, 0x01))
{
CreateBitField (BUF0, 0x0BE8, E8RW)
Store (Zero, E8RW)
}
If (PM6H)
{
CreateDWordField (BUF0, 0x01A9, ECLN)
Store (Zero, ECLN)
}
If (LEqual (PM6H, 0x01))
{
CreateBitField (BUF0, 0x0CC0, ECRW)
Store (Zero, ECRW)
}
If (PM0H)
{
CreateDWordField (BUF0, 0x01C4, F0LN)
Store (Zero, F0LN)
}
If (LEqual (PM0H, 0x01))
{
CreateBitField (BUF0, 0x0D98, F0RW)
Store (Zero, F0RW)
}
CreateDWordField (BUF0, 0x01D3, M1MN)
CreateDWordField (BUF0, 0x01D7, M1MX)
CreateDWordField (BUF0, 0x01DF, M1LN)
Multiply (0x02000000, DRB3, M1MN)
Add (Subtract (M1MX, M1MN), 0x01, M1LN)
ShiftRight (And (\_SB.PCI0.LPC0.MTSE, 0x0380), 0x07, Local0)
If (And (Local0, 0x04))
{
CreateDWordField (BUF0, 0x01EE, M2MN)
CreateDWordField (BUF0, 0x01F2, M2MX)
CreateDWordField (BUF0, 0x01FA, M2LN)
Store (0xFED00000, M2MN)
Store (0xFED003FF, M2MX)
Store (0x0400, M2LN)
If (LEqual (Local0, 0x05))
{
Store (0xFED01000, M2MN)
Store (0xFED013FF, M2MX)
}
If (LEqual (Local0, 0x06))
{
Store (0xFED02000, M2MN)
Store (0xFED023FF, M2MX)
}
If (LEqual (Local0, 0x07))
{
Store (0xFED03000, M2MN)
Store (0xFED033FF, M2MX)
}
}
Return (BUF0)
}
Name (_PRT, Package (0x0F)
{
Package (0x04)
{
0xFFFF,
0x00,
\_SB.PCI0.LPC0.LNKA,
0x00
},
Package (0x04)
{
0xFFFF,
0x01,
\_SB.PCI0.LPC0.LNKB,
0x00
},
Package (0x04)
{
0xFFFF,
0x02,
\_SB.PCI0.LPC0.LNKC,
0x00
},
Package (0x04)
{
0xFFFF,
0x03,
\_SB.PCI0.LPC0.LNKD,
0x00
},
Package (0x04)
{
0x0001FFFF,
0x00,
\_SB.PCI0.LPC0.LNKA,
0x00
},
Package (0x04)
{
0x001DFFFF,
0x00,
\_SB.PCI0.LPC0.LNKA,
0x00
},
Package (0x04)
{
0x001DFFFF,
0x01,
\_SB.PCI0.LPC0.LNKD,
0x00
},
Package (0x04)
{
0x001DFFFF,
0x02,
\_SB.PCI0.LPC0.LNKC,
0x00
},
Package (0x04)
{
0x001DFFFF,
0x03,
\_SB.PCI0.LPC0.LNKH,
0x00
},
Package (0x04)
{
0x001EFFFF,
0x00,
\_SB.PCI0.LPC0.LNKA,
0x00
},
Package (0x04)
{
0x001EFFFF,
0x01,
\_SB.PCI0.LPC0.LNKB,
0x00
},
Package (0x04)
{
0x001EFFFF,
0x02,
\_SB.PCI0.LPC0.LNKC,
0x00
},
Package (0x04)
{
0x001EFFFF,
0x03,
\_SB.PCI0.LPC0.LNKD,
0x00
},
Package (0x04)
{
0x001FFFFF,
0x00,
\_SB.PCI0.LPC0.LNKC,
0x00
},
Package (0x04)
{
0x001FFFFF,
0x01,
\_SB.PCI0.LPC0.LNKB,
0x00
}
})
Device (AGP)
{
Name (_ADR, 0x00010000)
Name (_PRT, Package (0x01)
{
Package (0x04)
{
0xFFFF,
0x00,
\_SB.PCI0.LPC0.LNKA,
0x00
}
})
Device (VGA)
{
Name (_ADR, 0x00)
Name (SWIT, 0x01)
Name (CRTA, 0x01)
Name (LCDA, 0x01)
Name (TV0A, 0x01)
Name (TOGF, 0x02)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_PSC, 0x00)
Name (USBF, 0x00)
Method (_PS0, 0, NotSerialized)
{
Store (0x00, _PSC)
}
Method (_PS3, 0, NotSerialized)
{
Store (0x03, _PSC)
}
Method (_DOS, 1, NotSerialized)
{
Store (And (Arg0, 0x03), SWIT)
}
Method (_DOD, 0, NotSerialized)
{
Return (Package (0x03)
{
0x00010100,
0x00010110,
0x00010200
})
}
Device (CRT)
{
Name (_ADR, 0x0100)
Method (_DCS, 0, NotSerialized)
{
If (CRTA)
{
Return (0x1F)
}
Else
{
Return (0x1D)
}
}
Method (_DGS, 0, NotSerialized)
{
If (CRTA)
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
Method (_DSS, 1, NotSerialized)
{
Store ("CRT --_DSS", Debug)
}
}
Device (TV0)
{
Name (_ADR, 0x0200)
Method (_DCS, 0, NotSerialized)
{
If (TV0A)
{
Return (0x1F)
}
Else
{
Return (0x1D)
}
}
Method (_DGS, 0, NotSerialized)
{
If (TV0A)
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
Method (_DSS, 1, NotSerialized)
{
Store ("TV --_DSS", Debug)
}
}
Device (LCD)
{
Name (_ADR, 0x0110)
Method (_DCS, 0, NotSerialized)
{
If (LCDA)
{
Return (0x1F)
}
Else
{
Return (0x1D)
}
}
Method (_DGS, 0, NotSerialized)
{
Store (LCDA, Local0)
If (LCDA)
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
Method (_DSS, 1, NotSerialized)
{
Store ("LCD --_DSS", Debug)
}
}
Method (SWIH, 0, NotSerialized)
{
Store (0x03, Local0)
If (LEqual (Local0, 0x03))
{
Increment (TOGF)
Store (TOGF, Local1)
If (LEqual (Local1, 0x01))
{
Store (One, LCDA)
Store (Zero, CRTA)
Store (Zero, TV0A)
}
Else
{
If (LEqual (Local1, 0x02))
{
Store (Zero, LCDA)
Store (One, CRTA)
Store (Zero, TV0A)
}
Else
{
If (LEqual (Local1, 0x03))
{
Store (One, LCDA)
Store (One, CRTA)
Store (Zero, TV0A)
}
Else
{
Store (One, TOGF)
Store (One, LCDA)
Store (Zero, CRTA)
Store (Zero, TV0A)
}
}
}
}
Else
{
If (LEqual (Local0, 0x05))
{
Increment (TOGF)
Store (TOGF, Local1)
If (LEqual (Local1, 0x01))
{
Store (One, LCDA)
Store (Zero, CRTA)
Store (Zero, TV0A)
}
Else
{
Store (Zero, TOGF)
Store (Zero, LCDA)
Store (Zero, CRTA)
Store (One, TV0A)
Store (Zero, TV0A)
}
}
Else
{
If (LEqual (Local0, 0x07))
{
Increment (TOGF)
Store (TOGF, Local1)
If (LEqual (Local1, 0x01))
{
Store (0x01, LCDA)
Store (0x00, CRTA)
Store (0x00, TV0A)
}
Else
{
If (LEqual (Local1, 0x02))
{
Store (0x00, LCDA)
Store (0x01, CRTA)
Store (0x00, TV0A)
}
Else
{
If (LEqual (Local1, 0x03))
{
Store (0x01, LCDA)
Store (0x01, CRTA)
Store (0x00, TV0A)
}
Else
{
Store (0x00, TOGF)
Store (0x00, LCDA)
Store (0x00, CRTA)
Store (0x01, TV0A)
Store (0x00, TV0A)
}
}
}
}
Else
{
Store (0x01, TOGF)
Store (0x01, LCDA)
Store (0x00, CRTA)
Store (0x00, TV0A)
}
}
}
Notify (\_SB.PCI0.AGP.VGA, 0x80)
}
Method (GETD, 0, NotSerialized)
{
Store (0x98, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
Store (\_SB.DISD, Local0)
If (LEqual (Local0, 0x01))
{
Store (0x01, TOGF)
}
If (LEqual (Local0, 0x02))
{
Store (0x02, TOGF)
}
If (LEqual (Local0, 0x03))
{
Store (0x03, TOGF)
}
If (LEqual (Local0, 0x04))
{
Store (0x00, TOGF)
}
}
}
}
Device (LPC0)
{
Name (_ADR, 0x001F0000)
Method (DECD, 4, NotSerialized)
{
Store (Arg0, Debug)
}
OperationRegion (REGS, PCI_Config, 0x40, 0xC0)
Field (REGS, DWordAcc, NoLock, Preserve)
{
PMBA, 16,
Offset (0x18),
GPBA, 16,
Offset (0x90),
POSD, 1,
Offset (0x91),
MTSE, 16,
Offset (0x94),
Offset (0xA0),
CMAD, 3,
, 1,
CMBD, 3,
Offset (0xA1),
LPTD, 2,
, 2,
FDDD, 1,
Offset (0xA6),
ECO1, 1,
ECO2, 1,
ELPT, 1,
EFDD, 1
}
OperationRegion (PIRX, PCI_Config, 0x60, 0x0C)
Field (PIRX, DWordAcc, NoLock, Preserve)
{
AccessAs (ByteAcc, 0x00),
PIRA, 8,
PIRB, 8,
PIRC, 8,
PIRD, 8,
Offset (0x08),
PIRE, 8,
PIRF, 8,
PIRG, 8,
PIRH, 8
}
Device (MBRD)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x1F)
Name (RSRC, ResourceTemplate ()
{
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
IO (Decode16, 0x0024, 0x0024, 0x01, 0x02)
IO (Decode16, 0x0028, 0x0028, 0x01, 0x02)
IO (Decode16, 0x002C, 0x002C, 0x01, 0x02)
IO (Decode16, 0x0030, 0x0030, 0x01, 0x02)
IO (Decode16, 0x0034, 0x0034, 0x01, 0x02)
IO (Decode16, 0x0038, 0x0038, 0x01, 0x02)
IO (Decode16, 0x003C, 0x003C, 0x01, 0x02)
IO (Decode16, 0x0050, 0x0050, 0x01, 0x04)
IO (Decode16, 0x0072, 0x0072, 0x01, 0x06)
IO (Decode16, 0x0080, 0x0080, 0x01, 0x01)
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
IO (Decode16, 0x00A4, 0x00A4, 0x01, 0x02)
IO (Decode16, 0x00A8, 0x00A8, 0x01, 0x02)
IO (Decode16, 0x00AC, 0x00AC, 0x01, 0x02)
IO (Decode16, 0x00B0, 0x00B0, 0x01, 0x06)
IO (Decode16, 0x00B8, 0x00B8, 0x01, 0x02)
IO (Decode16, 0x00BC, 0x00BC, 0x01, 0x02)
IO (Decode16, 0x1000, 0x1000, 0x01, 0x80)
IO (Decode16, 0x1180, 0x1180, 0x01, 0x40)
IO (Decode16, 0x01C0, 0x01C0, 0x01, 0x10)
IO (Decode16, 0x002E, 0x002E, 0x01, 0x02)
IO (Decode16, 0x004E, 0x004E, 0x01, 0x02)
IO (Decode16, 0x0068, 0x0068, 0x01, 0x01)
IO (Decode16, 0x006C, 0x006C, 0x01, 0x01)
IO (Decode16, 0xFE00, 0xFE00, 0x00, 0x01)
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02)
IO (Decode16, 0x0600, 0x0600, 0x01, 0x10)
IO (Decode16, 0x0610, 0x0610, 0x01, 0x10)
IO (Decode16, 0x0068, 0x0068, 0x01, 0x01)
IO (Decode16, 0x006C, 0x006C, 0x01, 0x01)
Memory32Fixed (ReadOnly, 0xFF800000, 0x00400000)
Memory32Fixed (ReadOnly, 0xFFF00000, 0x00100000)
Memory32Fixed (ReadWrite, 0x00000000, 0x000A0000)
Memory32Fixed (ReadOnly, 0x000E0000, 0x00020000)
Memory32Fixed (ReadWrite, 0x00100000, 0x00000000)
})
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x92, PMMN)
CreateWordField (RSRC, 0x94, PMMX)
And (^^PMBA, 0xFF80, PMMN)
Store (PMMN, PMMX)
CreateWordField (RSRC, 0x9A, GPMN)
CreateWordField (RSRC, 0x9C, GPMX)
And (^^GPBA, 0xFF80, GPMN)
Store (GPMN, GPMX)
CreateDWordField (RSRC, 0x0130, TMEM)
Store (\_SB.PCI0.DRB3, TMEM)
ShiftLeft (TMEM, 0x19, TMEM)
Subtract (TMEM, 0x00100000, TMEM)
Return (RSRC)
}
}
Device (DMAC)
{
Name (_HID, EisaId ("PNP0200"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
IO (Decode16, 0x0081, 0x0081, 0x01, 0x0F)
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
DMA (Compatibility, NotBusMaster, Transfer16) {4}
})
}
Device (MATH)
{
Name (_HID, EisaId ("PNP0C04"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x0F)
IRQ (Edge, ActiveHigh, Exclusive) {13}
})
}
Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
IRQ (Edge, ActiveHigh, Exclusive) {2}
})
}
Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0070, 0x0070, 0x01, 0x02)
IRQ (Edge, ActiveHigh, Exclusive) {8}
})
}
Device (SPKR)
{
Name (_HID, EisaId ("PNP0800"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
})
}
Device (TIME)
{
Name (_HID, EisaId ("PNP0100"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
IRQ (Edge, ActiveHigh, Exclusive) {0}
})
}
Device (LNKA)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x01)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {10}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRA, 0x80, PIRA)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRA, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRA, 0x70), PIRA)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRA, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
Device (LNKB)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x02)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {10}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRB, 0x80, PIRB)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRB, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRB, 0x70), PIRB)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRB, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
Device (LNKC)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x03)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {10}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRC, 0x80, PIRC)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRC, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRC, 0x70), PIRC)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRC, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
Device (LNKD)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x04)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {5}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRD, 0x80, PIRD)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRD, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRD, 0x70), PIRD)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRD, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
Device (LNKE)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x05)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {10}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Name (INES, 0x00)
Method (_DIS, 0, NotSerialized)
{
If (Or (LEqual (\_SB.PCI0.MYOS, 0x00), LEqual (\_SB.PCI0.MYOS, 0x02)))
{
Or (PIRE, 0x80, PIRE)
}
Else
{
Or (PIRE, 0x80, PIRE)
}
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRE, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRE, 0x70), PIRE)
Store (PIRE, INES)
}
Method (_STA, 0, NotSerialized)
{
If (Or (LEqual (\_SB.PCI0.MYOS, 0x00), LEqual (\_SB.PCI0.MYOS, 0x02)))
{
If (And (PIRE, 0x80))
{
Return (0x09)
}
}
Else
{
If (And (PIRE, 0x80))
{
Return (0x09)
}
}
Return (0x0B)
}
}
Device (LNKF)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x06)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {3,4,5,7,9,11,12}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRF, 0x80, PIRF)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRF, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRF, 0x70), PIRF)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRF, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
Device (LNKG)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x07)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {10}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRG, 0x80, PIRG)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRG, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRG, 0x70), PIRG)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRG, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
Device (LNKH)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x08)
Name (_PRS, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {10}
})
Name (RSRC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared) {}
})
Method (_DIS, 0, NotSerialized)
{
Or (PIRH, 0x80, PIRH)
}
Method (_CRS, 0, NotSerialized)
{
CreateWordField (RSRC, 0x01, IRQ0)
And (PIRH, 0x0F, Local0)
ShiftLeft (0x01, Local0, IRQ0)
Return (RSRC)
}
Method (_SRS, 1, NotSerialized)
{
CreateWordField (Arg0, 0x01, IRQ0)
FindSetRightBit (IRQ0, Local0)
Decrement (Local0)
Or (Local0, And (PIRH, 0x70), PIRH)
}
Method (_STA, 0, NotSerialized)
{
If (And (PIRH, 0x80))
{
Return (0x09)
}
Return (0x0B)
}
}
OperationRegion (GPOX, SystemIO, 0x1180, 0x40)
Field (GPOX, DWordAcc, Lock, Preserve)
{
Offset (0x07),
, 1,
IO25, 1,
, 1,
IO27, 1,
Offset (0x0E),
LV16, 1,
LV17, 1,
Offset (0x0F),
, 1,
LV25, 1,
, 1,
LV27, 1,
Offset (0x1B),
, 1,
BL25, 1,
, 1,
BL27, 1,
Offset (0x38),
RBID, 2,
LV34, 1,
LV35, 1,
LV36, 1,
LV37, 1,
LV38, 1,
LV39, 1
}
OperationRegion (PMIO, SystemIO, 0x1000, 0x51)
Field (PMIO, WordAcc, Lock, Preserve)
{
AccessAs (DWordAcc, 0x00),
Offset (0x29),
, 3,
PMES, 1,
Offset (0x2B),
, 3,
PMEE, 1,
Offset (0x2C),
GPI0, 1,
GPI1, 1,
GPI2, 1,
GPI3, 1,
GPI4, 1,
GPI5, 1,
GPI6, 1,
GPI7, 1,
GPI8, 1,
GPI9, 1,
GPIA, 1,
GPIB, 1,
GPIC, 1,
GPID, 1,
GPIE, 1,
GPIF, 1,
, 6,
GPEE, 1
}
Device (KBC)
{
Name (_HID, EisaId ("PNP0303"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags () {1}
})
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}
Device (MOUE)
{
Name (_HID, EisaId ("IBM3780"))
Name (_CID, 0x130FD041)
Name (_CRS, ResourceTemplate ()
{
IRQNoFlags () {12}
})
Method (_STA, 0, NotSerialized)
{
If (LEqual (SizeOf (\_OS), 0x14))
{
Return (0x00)
}
Else
{
If (\_SB.PS2M)
{
Return (0x0F)
}
Else
{
Return (0x00)
}
}
}
}
Device (MOU2)
{
Name (_HID, EisaId ("PNP0F13"))
Name (_CRS, ResourceTemplate ()
{
IRQNoFlags () {12}
})
Method (_STA, 0, NotSerialized)
{
If (LEqual (SizeOf (\_OS), 0x14))
{
If (\_SB.PS2M)
{
Return (0x0F)
}
Else
{
Return (0x00)
}
}
Else
{
Return (0x00)
}
}
}
Device (SIO)
{
Name (_HID, EisaId ("PNP0A05"))
OperationRegion (SIIO, SystemIO, 0x4E, 0x02)
Field (SIIO, ByteAcc, NoLock, Preserve)
{
INDX, 8,
DATA, 8
}
Mutex (N393, 0x00)
Method (SETD, 1, Serialized)
{
Store (0x07, INDX)
Store (Arg0, DATA)
}
Method (READ, 1, Serialized)
{
Store (Arg0, INDX)
Store (DATA, Local0)
Return (Local0)
}
Method (WRIT, 2, Serialized)
{
Store (Arg0, INDX)
Store (Arg1, DATA)
}
Method (LDRS, 3, NotSerialized)
{
Acquire (N393, 0xFFFF)
Store (0x07, INDX)
Store (Arg0, DATA)
Store (Arg1, INDX)
Store (Arg2, DATA)
Release (N393)
}
Method (LDRG, 2, NotSerialized)
{
Acquire (N393, 0xFFFF)
Store (0x07, INDX)
Store (Arg0, DATA)
Store (Arg1, INDX)
Store (DATA, Local0)
Release (N393)
Return (Local0)
}
Method (RCF6, 1, NotSerialized)
{
Acquire (N393, 0xFFFF)
Store (0x26, INDX)
Store (DATA, Local0)
And (Local0, Arg0, Local0)
Release (N393)
Return (XOr (Local0, Arg0))
}
Method (PDRS, 2, NotSerialized)
{
If (\_SB.PCI0.LPC0.POSD)
{
If (LEqual (Arg0, 0x00))
{
If (LEqual (Arg1, 0x03F0))
{
Store (0x00, Local0)
}
Else
{
If (LEqual (Arg1, 0x0370))
{
Store (0x01, Local0)
}
}
Store (Local0, \_SB.PCI0.LPC0.FDDD)
}
Else
{
If (LEqual (Arg0, 0x01))
{
If (LEqual (Arg1, 0x0378))
{
Store (0x00, Local0)
}
Else
{
If (LEqual (Arg1, 0x0278))
{
Store (0x01, Local0)
}
Else
{
If (LEqual (Arg1, 0x03BC))
{
Store (0x02, Local0)
}
}
}
Store (Local0, \_SB.PCI0.LPC0.LPTD)
}
Else
{
If (LEqual (Arg1, 0x03F8))
{
Store (0x00, Local0)
}
Else
{
If (LEqual (Arg1, 0x02F8))
{
Store (0x01, Local0)
}
Else
{
If (LEqual (Arg1, 0x0220))
{
Store (0x02, Local0)
}
Else
{
If (LEqual (Arg1, 0x0228))
{
Store (0x03, Local0)
}
Else
{
If (LEqual (Arg1, 0x0238))
{
Store (0x04, Local0)
}
Else
{
If (LEqual (Arg1, 0x02E8))
{
Store (0x05, Local0)
}
Else
{
If (LEqual (Arg1, 0x0338))
{
Store (0x06, Local0)
}
Else
{
If (LEqual (Arg1, 0x03E8))
{
Store (0x07, Local0)
}
}
}
}
}
}
}
}
If (LEqual (Arg0, 0x02))
{
Store (Local0, \_SB.PCI0.LPC0.CMBD)
}
Else
{
If (LEqual (Arg0, 0x03))
{
Store (Local0, \_SB.PCI0.LPC0.CMAD)
}
}
}
}
Return (0x01)
}
Else
{
Return (0x00)
}
}
Device (ECP)
{
Name (_HID, EisaId ("PNP0401"))
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized)
{
Store (LDRG (0x01, 0xF0), Local0)
ShiftRight (Local0, 0x05, Local0)
If (LAnd (RCF6 (0x02), LOr (LEqual (Local0, 0x04), LEqual (Local0, 0x07))))
{
ShiftLeft (LDRG (0x01, 0x30), 0x01, Local1)
Add (0x0D, Local1, Local1)
Return (Local1)
}
Else
{
Return (0x00)
}
}
Method (_PS0, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x01)
}
Method (_PS3, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_PRS, 0, NotSerialized)
{
Return (ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {5}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {5}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {7}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {5}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {5}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {7}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
EndDependentFn ()
})
}
Method (_DIS, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_CRS, 0, NotSerialized)
{
Name (DCRS, ResourceTemplate ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
})
Store (LDRG (0x01, 0x60), Local1)
Store (LDRG (0x01, 0x61), Local0)
Store (Local0, Index (DCRS, 0x02))
Store (Local0, Index (DCRS, 0x0A))
Store (Local0, Index (DCRS, 0x04))
Store (Local0, Index (DCRS, 0x0C))
Store (Local1, Index (DCRS, 0x03))
Store (Local1, Index (DCRS, 0x05))
Add (Local1, 0x04, Local1)
Store (Local1, Index (DCRS, 0x0B))
Store (Local1, Index (DCRS, 0x0D))
ShiftLeft (0x01, LDRG (0x01, 0x70), Local0)
Store (Local0, Index (DCRS, 0x11))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x12))
ShiftLeft (0x01, LDRG (0x01, 0x74), Local0)
Store (Local0, Index (DCRS, 0x14))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x15))
Return (DCRS)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, ADRL)
CreateByteField (Arg0, 0x03, ADRM)
CreateWordField (Arg0, 0x11, IRQM)
CreateWordField (Arg0, 0x14, DMAM)
FindSetRightBit (IRQM, Local0)
Decrement (Local0)
FindSetRightBit (DMAM, Local1)
Decrement (Local1)
LDRS (0x01, 0x70, Local0)
LDRS (0x01, 0x74, Local1)
LDRS (0x01, 0x60, ADRM)
LDRS (0x01, 0x61, ADRL)
LDRS (0x01, 0x30, 0x01)
}
}
Device (EPP)
{
Name (_HID, EisaId ("PNP0400"))
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
Store (LDRG (0x01, 0xF0), Local0)
ShiftRight (Local0, 0x05, Local0)
If (LAnd (RCF6 (0x02), LOr (LEqual (Local0, 0x02), LEqual (Local0, 0x03))))
{
ShiftLeft (LDRG (0x01, 0x30), 0x01, Local1)
Add (0x0D, Local1, Local1)
Return (Local1)
}
Else
{
Return (0x00)
}
}
Method (_PS0, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x01)
}
Method (_PS3, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_PRS, 0, NotSerialized)
{
Return (ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {5}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {5}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0178, 0x0178, 0x08, 0x08)
IO (Decode16, 0x0578, 0x0578, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0178, 0x0178, 0x08, 0x08)
IO (Decode16, 0x0578, 0x0578, 0x08, 0x08)
IRQNoFlags () {5}
}
EndDependentFn ()
})
}
Method (_DIS, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_CRS, 0, NotSerialized)
{
Name (DCRS, ResourceTemplate ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
})
Store (LDRG (0x01, 0x60), Local1)
Store (LDRG (0x01, 0x61), Local0)
Store (Local0, Index (DCRS, 0x02))
Store (Local0, Index (DCRS, 0x0A))
Store (Local0, Index (DCRS, 0x04))
Store (Local0, Index (DCRS, 0x0C))
Store (Local1, Index (DCRS, 0x03))
Store (Local1, Index (DCRS, 0x05))
Add (Local1, 0x04, Local1)
Store (Local1, Index (DCRS, 0x0B))
Store (Local1, Index (DCRS, 0x0D))
ShiftLeft (0x01, LDRG (0x01, 0x70), Local0)
Store (Local0, Index (DCRS, 0x11))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x12))
Return (DCRS)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, ADRL)
CreateByteField (Arg0, 0x03, ADRM)
CreateWordField (Arg0, 0x11, IRQM)
FindSetRightBit (IRQM, Local0)
Decrement (Local0)
LDRS (0x01, 0x70, Local0)
LDRS (0x01, 0x60, ADRM)
LDRS (0x01, 0x61, ADRL)
LDRS (0x01, 0x30, 0x01)
}
}
Device (LPTB)
{
Name (_HID, EisaId ("PNP0400"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
Store (LDRG (0x01, 0xF0), Local0)
ShiftRight (Local0, 0x05, Local0)
If (LAnd (RCF6 (0x02), LEqual (Local0, 0x01)))
{
ShiftLeft (LDRG (0x01, 0x30), 0x01, Local1)
Add (0x0D, Local1, Local1)
Return (Local1)
}
Else
{
Return (0x00)
}
}
Method (_PS0, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x01)
}
Method (_PS3, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_PRS, 0, NotSerialized)
{
Return (ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {5}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {5}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04)
IO (Decode16, 0x07BC, 0x07BC, 0x04, 0x04)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04)
IO (Decode16, 0x07BC, 0x07BC, 0x04, 0x04)
IRQNoFlags () {5}
}
EndDependentFn ()
})
}
Method (_DIS, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_CRS, 0, NotSerialized)
{
Name (DCRS, ResourceTemplate ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
})
Store (LDRG (0x01, 0x60), Local1)
Store (LDRG (0x01, 0x61), Local0)
Store (Local0, Index (DCRS, 0x02))
Store (Local0, Index (DCRS, 0x0A))
Store (Local0, Index (DCRS, 0x04))
Store (Local0, Index (DCRS, 0x0C))
Store (Local1, Index (DCRS, 0x03))
Store (Local1, Index (DCRS, 0x05))
Add (Local1, 0x04, Local1)
Store (Local1, Index (DCRS, 0x0B))
Store (Local1, Index (DCRS, 0x0D))
If (And (Local0, 0x04))
{
Store (0x04, Local0)
}
Else
{
Store (0x08, Local0)
}
Store (Local0, Index (DCRS, 0x06))
Store (Local0, Index (DCRS, 0x07))
Store (Local0, Index (DCRS, 0x0E))
Store (Local0, Index (DCRS, 0x0F))
ShiftLeft (0x01, LDRG (0x01, 0x70), Local0)
Store (Local0, Index (DCRS, 0x11))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x12))
Return (DCRS)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, ADRL)
CreateByteField (Arg0, 0x03, ADRM)
CreateWordField (Arg0, 0x11, IRQM)
FindSetRightBit (IRQM, Local0)
Decrement (Local0)
LDRS (0x01, 0x70, Local0)
LDRS (0x01, 0x60, ADRM)
LDRS (0x01, 0x61, ADRL)
LDRS (0x01, 0x30, 0x01)
}
}
Device (LPT)
{
Name (_HID, EisaId ("PNP0400"))
Name (_UID, 0x00)
Method (_STA, 0, NotSerialized)
{
Store (LDRG (0x01, 0xF0), Local0)
ShiftRight (Local0, 0x05, Local0)
If (LAnd (RCF6 (0x02), LEqual (Local0, 0x00)))
{
ShiftLeft (LDRG (0x01, 0x30), 0x01, Local1)
Add (0x0D, Local1, Local1)
Return (Local1)
}
Else
{
Return (0x00)
}
}
Method (_PS0, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x01)
}
Method (_PS3, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_PRS, 0, NotSerialized)
{
Return (ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {5}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {5}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x0278, 0x0278, 0x08, 0x08)
IO (Decode16, 0x0678, 0x0678, 0x08, 0x08)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04)
IO (Decode16, 0x07BC, 0x07BC, 0x04, 0x04)
IRQNoFlags () {7}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04)
IO (Decode16, 0x07BC, 0x07BC, 0x04, 0x04)
IRQNoFlags () {5}
}
EndDependentFn ()
})
}
Method (_DIS, 0, NotSerialized)
{
LDRS (0x01, 0x30, 0x00)
}
Method (_CRS, 0, NotSerialized)
{
Name (DCRS, ResourceTemplate ()
{
IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
IO (Decode16, 0x0778, 0x0778, 0x08, 0x08)
IRQNoFlags () {7}
})
Store (LDRG (0x01, 0x60), Local1)
Store (LDRG (0x01, 0x61), Local0)
Store (Local0, Index (DCRS, 0x02))
Store (Local0, Index (DCRS, 0x0A))
Store (Local0, Index (DCRS, 0x04))
Store (Local0, Index (DCRS, 0x0C))
Store (Local1, Index (DCRS, 0x03))
Store (Local1, Index (DCRS, 0x05))
Add (Local1, 0x04, Local1)
Store (Local1, Index (DCRS, 0x0B))
Store (Local1, Index (DCRS, 0x0D))
If (And (Local0, 0x04))
{
Store (0x04, Local0)
}
Else
{
Store (0x08, Local0)
}
Store (Local0, Index (DCRS, 0x06))
Store (Local0, Index (DCRS, 0x07))
Store (Local0, Index (DCRS, 0x0E))
Store (Local0, Index (DCRS, 0x0F))
ShiftLeft (0x01, LDRG (0x01, 0x70), Local0)
Store (Local0, Index (DCRS, 0x11))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x12))
Return (DCRS)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, ADRL)
CreateByteField (Arg0, 0x03, ADRM)
CreateWordField (Arg0, 0x11, IRQM)
FindSetRightBit (IRQM, Local0)
Decrement (Local0)
LDRS (0x01, 0x70, Local0)
LDRS (0x01, 0x60, ADRM)
LDRS (0x01, 0x61, ADRL)
LDRS (0x01, 0x30, 0x01)
}
}
Device (COMA)
{
Name (_HID, EisaId ("PNP0501"))
Name (_UID, 0x00)
Method (_STA, 0, NotSerialized)
{
If (RCF6 (0x08))
{
ShiftLeft (LDRG (0x03, 0x30), 0x01, Local1)
Add (0x0D, Local1, Local1)
Return (Local1)
}
Else
{
Return (0x00)
}
}
Method (_PS0, 0, NotSerialized)
{
LDRS (0x03, 0x30, 0x01)
}
Method (_PS3, 0, NotSerialized)
{
LDRS (0x03, 0x30, 0x00)
}
Method (_PRS, 0, NotSerialized)
{
Return (ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {4}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {4}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {4}
}
EndDependentFn ()
})
}
Method (_DIS, 0, NotSerialized)
{
LDRS (0x03, 0x30, 0x00)
}
Method (_CRS, 0, NotSerialized)
{
Name (DCRS, ResourceTemplate ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
})
Store (LDRG (0x03, 0x60), Local1)
Store (LDRG (0x03, 0x61), Local0)
Store (Local0, Index (DCRS, 0x02))
Store (Local0, Index (DCRS, 0x04))
Store (Local1, Index (DCRS, 0x03))
Store (Local1, Index (DCRS, 0x05))
ShiftLeft (0x01, LDRG (0x03, 0x70), Local0)
Store (Local0, Index (DCRS, 0x09))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x0A))
Return (DCRS)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, ADRL)
CreateByteField (Arg0, 0x03, ADRM)
CreateWordField (Arg0, 0x09, IRQM)
FindSetRightBit (IRQM, Local0)
Decrement (Local0)
LDRS (0x03, 0x70, Local0)
LDRS (0x03, 0x60, ADRM)
LDRS (0x03, 0x61, ADRL)
LDRS (0x03, 0x30, 0x01)
}
}
Device (FIR)
{
Method (_HID, 0, NotSerialized)
{
If (LOr (LEqual (MYOS, 0x01), LEqual (MYOS, 0x03)))
{
Return (0x0160633A)
}
Else
{
Return (0x0160633A)
}
}
Name (_UID, 0x00)
Method (_STA, 0, NotSerialized)
{
Store (LDRG (0x02, 0x74), Local0)
If (LAnd (RCF6 (0x04), LNot (LEqual (Local0, 0x04))))
{
ShiftLeft (LDRG (0x02, 0x30), 0x01, Local1)
Add (0x0D, Local1, Local1)
Return (Local1)
}
Else
{
Return (0x00)
}
}
Method (_PS0, 0, NotSerialized)
{
LDRS (0x02, 0x30, 0x01)
}
Method (_PS3, 0, NotSerialized)
{
LDRS (0x02, 0x30, 0x00)
}
Method (_PRS, 0, NotSerialized)
{
Return (ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {1}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
StartDependentFnNoPri ()
{
IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08)
IRQNoFlags () {4}
DMA (Compatibility, NotBusMaster, Transfer8) {3}
}
EndDependentFn ()
})
}
Method (_DIS, 0, NotSerialized)
{
LDRS (0x02, 0x30, 0x00)
Store (0x00, \_SB.PCI0.LPC0.ECO1)
}
Method (_CRS, 0, NotSerialized)
{
Name (DCRS, ResourceTemplate ()
{
IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
IRQNoFlags () {3}
DMA (Compatibility, NotBusMaster, Transfer8) {0}
})
Store (LDRG (0x02, 0x60), Local1)
Store (LDRG (0x02, 0x61), Local0)
Store (Local0, Index (DCRS, 0x02))
Store (Local0, Index (DCRS, 0x04))
Store (Local1, Index (DCRS, 0x03))
Store (Local1, Index (DCRS, 0x05))
ShiftLeft (0x01, LDRG (0x02, 0x70), Local0)
Store (Local0, Index (DCRS, 0x09))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x0A))
ShiftLeft (0x01, LDRG (0x02, 0x74), Local0)
Store (Local0, Index (DCRS, 0x0C))
ShiftRight (Local0, 0x08, Local1)
Store (Local1, Index (DCRS, 0x0D))
Return (DCRS)
}
Method (_SRS, 1, NotSerialized)
{
Store (0x01, \_SB.PCI0.LPC0.ECO1)
CreateByteField (Arg0, 0x02, ADRL)
CreateByteField (Arg0, 0x03, ADRM)
CreateWordField (Arg0, 0x09, IRQM)
CreateWordField (Arg0, 0x0C, DMAM)
FindSetRightBit (IRQM, Local0)
Decrement (Local0)
FindSetRightBit (DMAM, Local1)
Decrement (Local1)
LDRS (0x02, 0x70, Local0)
LDRS (0x02, 0x74, Local1)
LDRS (0x02, 0x60, ADRM)
LDRS (0x02, 0x61, ADRL)
PDRS (0x02, Add (ShiftLeft (ADRM, 0x08), ADRL))
LDRS (0x02, 0x30, 0x01)
}
}
}
Device (EC0)
{
Name (_HID, EisaId ("PNP0C09"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x0062, 0x0062, 0x01, 0x01)
IO (Decode16, 0x0066, 0x0066, 0x01, 0x01)
})
Name (_GPE, 0x1D)
Name (OSEJ, 0x00)
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x03))
{
Store (Arg1, \_SB.OKEC)
If (Or (LEqual (\_SB.PCI0.MYOS, 0x03), LEqual (\_SB.PCI0.MYOS, 0x01)))
{
If (Arg1)
{
Store (0x01, \_SB.PCI0.LPC0.EC0.RG57)
}
}
}
}
OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x04),
CMCM, 8,
CMD1, 8,
CMD2, 8,
CMD3, 8,
Offset (0x18),
SMPR, 8,
SMST, 8,
SMAD, 8,
SMCM, 8,
SMD0, 256,
BCNT, 8,
SMAA, 8,
BATD, 16,
ACDF, 1,
Offset (0x41),
, 4,
FPR1, 1,
S4LD, 1,
S5LW, 1,
PFLG, 1,
Offset (0x43),
TMSS, 2,
, 2,
BANK, 4,
Offset (0x45),
VFAN, 1,
Offset (0x46),
RL01, 1,
RD01, 1,
RF01, 1,
RP01, 1,
RB01, 1,
RC01, 1,
, 1,
R701, 1,
R801, 1,
RM01, 1,
RI01, 1,
, 1,
, 1,
, 1,
RA01, 1,
RR01, 1,
RL10, 1,
RD10, 1,
RF10, 1,
RP10, 1,
RB10, 1,
RC10, 1,
, 1,
R710, 1,
R810, 1,
RM10, 1,
RI10, 1,
, 1,
, 1,
, 1,
RA10, 1,
RR10, 1,
WL01, 1,
WD01, 1,
WF01, 1,
WP01, 1,
WB01, 1,
WC01, 1,
, 1,
W701, 1,
W801, 1,
WM01, 1,
WI01, 1,
, 1,
, 1,
, 1,
WA01, 1,
WR01, 1,
WL10, 1,
WD10, 1,
WF10, 1,
WP10, 1,
WB10, 1,
WC10, 1,
, 1,
W710, 1,
W810, 1,
WM10, 1,
WI10, 1,
, 1,
, 1,
, 1,
WA10, 1,
WR10, 1,
LIDE, 1,
BAYE, 1,
EFDE, 1,
PRDE, 1,
BRBE, 1,
CRTE, 1,
, 1,
W7BE, 1,
W8BE, 1,
PMEE, 1,
INTE, 1,
, 1,
, 1,
, 1,
DB2E, 1,
DB3E, 1,
Offset (0x52),
LIDS, 1,
BAYS, 1,
EFDS, 1,
PRDS, 1,
BRBS, 1,
CRTS, 1,
, 1,
W7BS, 1,
W8BS, 1,
DPEM, 1,
DINT, 1,
, 1,
, 1,
, 1,
DB2S, 1,
DB3S, 1,
Offset (0x57),
RG57, 8,
CTMP, 8,
RG59, 8,
RG5A, 8,
RG5B, 8,
FSPD, 16,
Offset (0x5F),
FAN2, 1,
SFN2, 1,
Offset (0x60),
, 1,
FANC, 1,
Offset (0x70),
MBID, 8,
MBTS, 1,
MBTF, 1,
Offset (0x72),
MBTC, 1,
Offset (0x77),
BA1C, 8,
MBVG, 16,
MCUR, 16,
Offset (0x80),
SBID, 8,
SBTS, 1,
SBTF, 1,
Offset (0x82),
SBTC, 1,
Offset (0x87),
BA2C, 8,
ABVG, 16,
ACUR, 16,
Offset (0xC3),
MBRM, 16,
Offset (0xCA),
ABRM, 16,
Offset (0xD0),
EBPL, 1,
Offset (0xD2),
, 6,
APWR, 1,
Offset (0xD6),
DBPL, 8,
Offset (0xE7),
GQKS, 7
}
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x1C),
SMW0, 16
}
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x1C),
SMB0, 8
}
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x1C),
FLD0, 64
}
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x1C),
FLD1, 128
}
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x1C),
FLD2, 192
}
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x1C),
FLD3, 256
}
Mutex (MUT0, 0x00)
Method (SMRD, 4, NotSerialized)
{
If (LNot (\_SB.OKEC))
{
Return (0xFF)
}
If (LNot (LEqual (Arg0, 0x07)))
{
If (LNot (LEqual (Arg0, 0x09)))
{
If (LNot (LEqual (Arg0, 0x0B)))
{
Return (0x19)
}
}
}
Acquire (MUT0, 0xFFFF)
Store (0x04, Local0)
While (LGreater (Local0, 0x01))
{
And (SMST, 0x40, SMST)
Store (Arg2, SMCM)
Store (Arg1, SMAD)
Store (Arg0, SMPR)
Store (0x00, Local3)
While (LNot (And (SMST, 0xBF, Local1)))
{
Sleep (0x02)
Increment (Local3)
If (LEqual (Local3, 0x32))
{
And (SMST, 0x40, SMST)
Store (Arg2, SMCM)
Store (Arg1, SMAD)
Store (Arg0, SMPR)
Store (0x00, Local3)
}
}
If (LEqual (Local1, 0x80))
{
Store (0x00, Local0)
}
Else
{
Decrement (Local0)
}
}
If (Local0)
{
Store (And (Local1, 0x1F), Local0)
}
Else
{
If (LEqual (Arg0, 0x07))
{
Store (SMB0, Arg3)
}
If (LEqual (Arg0, 0x09))
{
Store (SMW0, Arg3)
}
If (LEqual (Arg0, 0x0B))
{
Store (BCNT, Local3)
ShiftRight (0x0100, 0x03, Local2)
If (LGreater (Local3, Local2))
{
Store (Local2, Local3)
}
If (LLess (Local3, 0x09))
{
Store (FLD0, Local2)
}
Else
{
If (LLess (Local3, 0x11))
{
Store (FLD1, Local2)
}
Else
{
If (LLess (Local3, 0x19))
{
Store (FLD2, Local2)
}
Else
{
Store (FLD3, Local2)
}
}
}
Increment (Local3)
Store (Buffer (Local3) {}, Local4)
Decrement (Local3)
Store (Zero, Local5)
While (LGreater (Local3, Local5))
{
GBFE (Local2, Local5, RefOf (Local6))
PBFE (Local4, Local5, Local6)
Increment (Local5)
}
PBFE (Local4, Local5, 0x00)
Store (Local4, Arg3)
}
}
Release (MUT0)
Return (Local0)
}
Method (SMWR, 4, NotSerialized)
{
If (LNot (\_SB.OKEC))
{
Return (0xFF)
}
If (LNot (LEqual (Arg0, 0x06)))
{
If (LNot (LEqual (Arg0, 0x08)))
{
If (LNot (LEqual (Arg0, 0x0A)))
{
Return (0x19)
}
}
}
Acquire (MUT0, 0xFFFF)
Store (0x04, Local0)
While (LGreater (Local0, 0x01))
{
If (LEqual (Arg0, 0x06))
{
Store (Arg3, SMB0)
}
If (LEqual (Arg0, 0x08))
{
Store (Arg3, SMW0)
}
If (LEqual (Arg0, 0x0A))
{
Store (Arg3, SMD0)
}
And (SMST, 0x40, SMST)
Store (Arg2, SMCM)
Store (Arg1, SMAD)
Store (Arg0, SMPR)
Store (0x00, Local3)
While (LNot (And (SMST, 0xBF, Local1)))
{
Sleep (0x02)
Increment (Local3)
If (LEqual (Local3, 0x32))
{
And (SMST, 0x40, SMST)
Store (Arg2, SMCM)
Store (Arg1, SMAD)
Store (Arg0, SMPR)
Store (0x00, Local3)
}
}
If (LEqual (Local1, 0x80))
{
Store (0x00, Local0)
}
Else
{
Decrement (Local0)
}
}
If (Local0)
{
Store (And (Local1, 0x1F), Local0)
}
Release (MUT0)
Return (Local0)
}
Method (BPOL, 1, NotSerialized)
{
Store (Arg0, DBPL)
Store (0x01, EBPL)
}
Name (ECUS, 0x00)
Name (BATO, 0x00)
Name (BATN, 0x00)
Name (BATF, 0xC0)
Method (_Q09, 0, NotSerialized)
{
If (LEqual (SizeOf (\_OS), 0x14))
{
Notify (\_SB.BAT1, 0x80)
Notify (\_SB.BAT1, 0x00)
Notify (\_SB.BAT2, 0x80)
Notify (\_SB.BAT2, 0x00)
Notify (\_SB.ACAD, 0x00)
}
If (LEqual (SizeOf (\_OS), 0x14))
{
BPOL (0x3C)
}
}
Method (_Q20, 0, NotSerialized)
{
If (And (SMST, 0x40))
{
Store (SMAA, Local0)
If (LEqual (Local0, 0x14))
{
SELE ()
If (And (0x40, BATF))
{
Notify (\_SB.BAT1, 0x81)
}
If (And (0x80, BATF))
{
Notify (\_SB.BAT2, 0x81)
}
If (And (0x02, BATF))
{
Notify (\_SB.ACAD, 0x80)
}
Notify (\_SB.BAT1, 0x80)
Notify (\_SB.BAT2, 0x80)
Store (BATD, BATO)
And (SMST, 0xBF, SMST)
}
}
}
Method (SELE, 0, NotSerialized)
{
Store (BATD, BATN)
Store (0x00, BATF)
If (And (0xC0, BATN))
{
Or (BATF, 0x01, BATF)
}
If (And (0x0300, BATN))
{
Or (BATF, 0x04, BATF)
}
And (BATN, 0x01, Local0)
And (BATO, 0x01, Local1)
If (Local0)
{
Or (BATF, 0x0100, BATF)
}
Else
{
And (BATF, 0xFEFF, BATF)
}
If (Not (LEqual (Local0, Local1)))
{
Or (BATF, 0x40, BATF)
}
And (BATN, 0x02, Local0)
And (BATO, 0x02, Local1)
If (Local0)
{
Or (BATF, 0x0200, BATF)
}
Else
{
And (BATF, 0xFDFF, BATF)
}
If (Not (LEqual (Local0, Local1)))
{
Or (BATF, 0x80, BATF)
}
And (BATN, 0xC0, Local0)
And (BATO, 0xC0, Local1)
If (Not (LEqual (Local0, Local1)))
{
Or (BATF, 0x02, BATF)
}
If (And (0x01, BATF))
{
If (And (0x04, BATF))
{
If (And (BATN, 0x20))
{
Or (BATF, 0x10, BATF)
}
Else
{
Or (BATF, 0x20, BATF)
}
}
}
}
Method (_Q0D, 0, NotSerialized)
{
Store ("Sleep Button Query: Fn+F4", Debug)
Notify (\_SB.SLPB, 0x80)
}
Method (_Q0E, 0, NotSerialized)
{
\_SB.PCI0.AGP.VGA.SWIH ()
}
Method (_Q0F, 0, NotSerialized)
{
Store ("Display blank: Fn+F6", Debug)
Not (LV16, Local0)
Store (Local0, LV16)
}
Method (_Q13, 0, NotSerialized)
{
Store ("Brightness Up: Fn+->", Debug)
Store (0x8C, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
Method (_Q12, 0, NotSerialized)
{
Store ("Brightness Down: Fn+<-", Debug)
Store (0x8D, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
Method (_Q80, 0, NotSerialized)
{
Store ("Temperature increasing: _Q80", Debug)
Notify (\_TZ.THRM, 0x80)
}
Method (_Q81, 0, NotSerialized)
{
Store ("Temperature decreasing: _Q81", Debug)
Notify (\_TZ.THRM, 0x80)
}
Event (EJT1)
Method (_Q8A, 0, NotSerialized)
{
Mutex (MUT0, 0x00)
Mutex (MUT1, 0x00)
Store ("------------------_Q0x8A --------------------------------------", Debug)
If (LIDE)
{
Store (0x01, LIDE)
Notify (\_SB.LID, 0x80)
}
If (DB2E)
{
Store ("-------- Device R-Bay Event ------", Debug)
Store (0x01, DB2E)
If (Or (LEqual (\_SB.PCI0.MYOS, 0x01), LEqual (\_SB.PCI0.MYOS, 0x03)))
{
If (DB2S)
{
Store ("----------- Device Bay Change Status ---------- IN ", Debug)
Store (\_SB.PCI0.LPC0.RBID, Local0)
Store (Local0, \_SB.PCI0.IDE0.BAYR)
If (LEqual (Local0, 0x00))
{
Store (0x00, \_SB.PCI0.LPC0.LV37)
}
Else
{
Store (0x00, \_SB.PCI0.LPC0.LV37)
Store (0x00, \_SB.PCI0.LPC0.LV39)
Sleep (0x32)
Store (0x01, \_SB.PCI0.LPC0.LV39)
Sleep (0x09C4)
Store (0x01, \_SB.PCI0.IDE0.SSIG)
Store (0x01, \_SB.PCI0.IDE0.UDC1)
Store (0x02, \_SB.PCI0.IDE0.UDT1)
Or (\_SB.PCI0.IDE0.FSCB, 0x04, \_SB.PCI0.IDE0.FSCB)
Store (0xE303, \_SB.PCI0.IDE0.ITM1)
Store (0x00, \_SB.PCI0.IDE0.SSIG)
Notify (\_SB.PCI0.IDE0.SECN.BAY1, 0x00)
}
}
Else
{
Store ("-------- Device Bay Event ------ OUT ", Debug)
Store (\_SB.PCI0.IDE0.BAYR, Local0)
Store (0x01, \_SB.PCI0.LPC0.LV37)
If (Or (LEqual (Local0, 0x01), LEqual (Local0, 0x02)))
{
Notify (\_SB.PCI0.IDE0.SECN.BAY1, 0x01)
}
}
}
}
}
}
OperationRegion (SMI0, SystemIO, 0x0000FE00, 0x00000002)
Field (SMI0, AnyAcc, NoLock, Preserve)
{
SMIC, 8
}
OperationRegion (SMI1, SystemMemory, 0x1FF7BEBD, 0x00000090)
Field (SMI1, AnyAcc, NoLock, Preserve)
{
BCMD, 8,
DID, 32,
INFO, 1024
}
Field (SMI1, AnyAcc, NoLock, Preserve)
{
AccessAs (ByteAcc, 0x00),
Offset (0x05),
INF, 8
}
}
Device (MDM0)
{
Name (_ADR, 0x001F0006)
Name (_PRW, Package (0x02)
{
0x05,
0x03
})
}
Device (HUB)
{
Name (_ADR, 0x001E0000)
Name (_PRT, Package (0x05)
{
Package (0x04)
{
0x0002FFFF,
0x00,
\_SB.PCI0.LPC0.LNKD,
0x00
},
Package (0x04)
{
0x0004FFFF,
0x00,
\_SB.PCI0.LPC0.LNKE,
0x00
},
Package (0x04)
{
0x0004FFFF,
0x01,
\_SB.PCI0.LPC0.LNKF,
0x00
},
Package (0x04)
{
0x0006FFFF,
0x00,
\_SB.PCI0.LPC0.LNKB,
0x00
},
Package (0x04)
{
0x0007FFFF,
0x00,
\_SB.PCI0.LPC0.LNKC,
0x00
}
})
Device (GLAN)
{
Name (_ADR, 0x00020000)
Name (_PRW, Package (0x02)
{
0x0B,
0x05
})
}
}
Device (IDE0)
{
Name (_ADR, 0x001F0001)
OperationRegion (PCI, PCI_Config, 0x00, 0x58)
Field (PCI, DWordAcc, NoLock, Preserve)
{
Offset (0x03),
, 7,
SIDE, 1,
Offset (0x42),
, 1,
EIOR, 1,
, 13,
ESID, 1,
Offset (0x48),
UMA0, 1,
UMA1, 1,
UMA2, 1,
UMA3, 1,
Offset (0x56),
PSIG, 2,
SSIG, 2
}
Field (PCI, DWordAcc, NoLock, Preserve)
{
Offset (0x40),
ITM0, 16,
ITM1, 16,
SIT0, 4,
SIT1, 4,
Offset (0x48),
UDC0, 2,
UDC1, 2,
Offset (0x4A),
UDT0, 8,
UDT1, 8,
Offset (0x54),
ICF0, 2,
ICF1, 2,
CB80, 4,
, 2,
WPPE, 1,
, 1,
FSCB, 4,
TRIP, 2,
TRIS, 2,
FATS, 4
}
Name (TIM0, Package (0x01)
{
Package (0x05)
{
0x78,
0xB4,
0xF0,
0x0186,
0x0258
}
})
Name (TIM1, Package (0x01)
{
Package (0x03)
{
0x78,
0x96,
0x01FE
}
})
Name (TIM2, Package (0x01)
{
Package (0x06)
{
0x18,
0x1E,
0x2D,
0x3C,
0x5A,
0x78
}
})
Name (AT01, Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
})
Name (AT02, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
})
Name (AT03, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
})
Name (AT04, Buffer (0x07)
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
})
Name (ATA0, Buffer (0x1D) {})
Name (ATA1, Buffer (0x1D) {})
Name (ATA2, Buffer (0x1D) {})
Name (ATA3, Buffer (0x1D) {})
Name (ATAB, Buffer (0x0E) {})
Name (CMDC, 0x00)
Name (BAYR, 0x00)
Method (_INI, 0, NotSerialized)
{
Store (\_SB.PCI0.LPC0.RBID, BAYR)
}
Method (GTFB, 3, Serialized)
{
Multiply (CMDC, 0x38, Local0)
CreateField (ATAB, Local0, 0x38, CMDX)
Multiply (CMDC, 0x07, Local0)
CreateByteField (ATAB, Add (Local0, 0x01), A001)
CreateByteField (ATAB, Add (Local0, 0x05), A005)
Store (Arg0, CMDX)
Store (Arg1, A001)
Store (Arg2, A005)
Increment (CMDC)
}
Mutex (GTFM, 0x00)
Method (GTF, 3, Serialized)
{
Acquire (GTFM, 0xFFFF)
CreateDWordField (Arg2, 0x00, PIO0)
CreateDWordField (Arg2, 0x04, DMA0)
CreateDWordField (Arg2, 0x08, PIO1)
CreateDWordField (Arg2, 0x0C, DMA1)
CreateDWordField (Arg2, 0x10, CHNF)
Store (0x00, CMDC)
Name (ID00, 0x80)
Name (ID49, 0x0C00)
Name (ID59, 0x00)
Name (ID53, 0x04)
Name (ID63, 0x0F00)
Name (ID88, 0x0F00)
Name (IRDY, 0x01)
Name (PIOT, 0x00)
Name (DMAT, 0x00)
If (LEqual (SizeOf (Arg1), 0x0200))
{
CreateByteField (Arg1, 0x00, IB00)
Store (IB00, ID00)
CreateWordField (Arg1, 0x62, IW49)
Store (IW49, ID49)
CreateWordField (Arg1, 0x6A, IW53)
Store (IW53, ID53)
CreateWordField (Arg1, 0x7E, IW63)
Store (IW63, ID63)
CreateWordField (Arg1, 0x76, IW59)
Store (IW59, ID59)
CreateWordField (Arg1, 0xB0, IW88)
Store (IW88, ID88)
}
Else
{
Return (ATAB)
}
Store (0xA0, Local7)
If (Arg0)
{
Store (0xB0, Local7)
And (CHNF, 0x08, IRDY)
If (And (CHNF, 0x10))
{
Store (PIO1, PIOT)
}
Else
{
Store (PIO0, PIOT)
}
If (And (CHNF, 0x04))
{
If (And (CHNF, 0x10))
{
Store (DMA1, DMAT)
}
Else
{
Store (DMA0, DMAT)
}
}
}
Else
{
And (CHNF, 0x02, IRDY)
Store (PIO0, PIOT)
If (And (CHNF, 0x01))
{
Store (DMA0, DMAT)
}
}
If (LAnd (And (ID53, 0x04), And (ID88, 0xFF)))
{
Store (0x00, Local1)
And (ID88, 0xFF, Local2)
While (ShiftRight (Local2, Local1))
{
Increment (Local1)
}
Decrement (Local1)
GTFB (AT01, Or (0x40, Local1), Local7)
}
If (IRDY)
{
Store (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, 0x00, 0x00), Local1)
If (LEqual (Local1, Ones))
{
Store (0x04, Local1)
}
Subtract (0x04, Local1, Local1)
GTFB (AT01, Or (0x08, Local1), Local7)
}
Else
{
If (And (ID49, 0x0400))
{
GTFB (AT01, 0x01, Local7)
}
}
Release (GTFM)
Return (ATAB)
}
Method (RATA, 1, NotSerialized)
{
CreateByteField (Arg0, 0x00, CMDN)
Multiply (CMDN, 0x38, Local0)
CreateField (Arg0, 0x08, Local0, RETB)
Return (RETB)
}
Name (REGF, 0x01)
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x02))
{
Store (Arg1, REGF)
}
}
Name (BAYD, 0x00)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Method (GTM, 6, NotSerialized)
{
Store (Buffer (0x14) {}, Local0)
CreateDWordField (Local0, 0x00, PIO0)
CreateDWordField (Local0, 0x04, DMA0)
CreateDWordField (Local0, 0x08, PIO1)
CreateDWordField (Local0, 0x0C, DMA1)
CreateDWordField (Local0, 0x10, FLAG)
If (LOr (And (Arg0, 0x08), LNot (And (Arg0, 0x01))))
{
Store (0x0384, PIO0)
}
Else
{
Add (ShiftRight (And (Arg0, 0x0300), 0x08), ShiftRight (And (Arg0, 0x3000), 0x0C), Local1)
Multiply (Subtract (0x09, Local1), 0x1E, PIO0)
}
If (And (Arg0, 0x4000))
{
If (LOr (And (Arg0, 0x80), LNot (And (Arg0, 0x10))))
{
Store (0x0384, PIO1)
}
Else
{
Add (And (Arg1, 0x03), ShiftRight (And (Arg1, 0x0C), 0x02), Local1)
Multiply (Subtract (0x09, Local1), 0x1E, PIO1)
}
}
Else
{
Store (PIO0, PIO1)
}
If (And (Arg2, 0x01))
{
If (And (Arg5, 0x01))
{
Store (0x08, DMA0)
}
Else
{
Subtract (0x04, And (Arg3, 0x03), Local1)
If (And (Arg4, 0x01))
{
Multiply (Local1, 0x0F, DMA0)
}
Else
{
Multiply (Local1, 0x1E, DMA0)
}
}
}
Else
{
Store (PIO0, DMA0)
}
If (And (Arg0, 0x4000))
{
If (And (Arg2, 0x02))
{
If (And (Arg5, 0x02))
{
Store (0x08, DMA1)
}
Else
{
Subtract (0x04, ShiftRight (And (Arg3, 0x30), 0x04), Local1)
If (And (Arg4, 0x02))
{
Multiply (Local1, 0x0F, DMA1)
}
Else
{
Multiply (Local1, 0x1E, DMA1)
}
}
}
Else
{
Store (PIO1, DMA1)
}
}
Else
{
Store (DMA0, DMA1)
}
Store (Zero, FLAG)
If (And (Arg0, 0x01))
{
Or (FLAG, 0x10, FLAG)
}
If (And (Arg2, 0x01))
{
Or (FLAG, 0x01, FLAG)
}
If (And (Arg0, 0x02))
{
Or (FLAG, 0x02, FLAG)
}
If (And (Arg2, 0x02))
{
Or (FLAG, 0x04, FLAG)
}
If (And (Arg0, 0x20))
{
Or (FLAG, 0x08, FLAG)
}
Return (Local0)
}
Method (STMS, 3, NotSerialized)
{
Store (Buffer (0x18) {}, Local7)
CreateDWordField (Local7, 0x00, ITM)
CreateDWordField (Local7, 0x04, SIT)
CreateDWordField (Local7, 0x08, UDC)
CreateDWordField (Local7, 0x0C, UDT)
CreateDWordField (Local7, 0x10, ICF)
CreateDWordField (Local7, 0x14, A100)
Store (0x01, WPPE)
CreateDWordField (Arg0, 0x00, PIO0)
CreateDWordField (Arg0, 0x04, DMA0)
CreateDWordField (Arg0, 0x08, PIO1)
CreateDWordField (Arg0, 0x0C, DMA1)
CreateDWordField (Arg0, 0x10, FLAG)
Store (FLAG, Local4)
Store (0x4000, Local0)
Name (W49M, 0x00)
Name (W53M, 0x00)
Name (W62M, 0x00)
Name (W64M, 0x00)
Name (W88M, 0x00)
If (LEqual (SizeOf (Arg1), 0x0200))
{
CreateDWordField (Arg1, 0x00, W00A)
CreateDWordField (Arg1, 0x62, W49A)
CreateDWordField (Arg1, 0x6A, W53A)
CreateDWordField (Arg1, 0x7C, W62A)
CreateDWordField (Arg1, 0x80, W64A)
CreateDWordField (Arg1, 0xB0, W88A)
Store (W49A, W49M)
Store (W53A, W53M)
Store (W62A, W62M)
Store (W64A, W64M)
Store (W88A, W88M)
If (W00A)
{
Or (Local0, 0x8000, Local0)
}
If (LNot (And (W00A, 0x80)))
{
Or (Local0, 0x04, Local0)
}
}
Else
{
Store (0x00, W49M)
Store (0x00, W53M)
Store (0x00, W62M)
Store (0x00, W64M)
Store (0x00, W88M)
}
Name (W49S, 0x00)
Name (W53S, 0x00)
Name (W62S, 0x00)
Name (W64S, 0x00)
Name (W88S, 0x00)
If (LEqual (SizeOf (Arg2), 0x0200))
{
CreateDWordField (Arg2, 0x00, W00B)
CreateDWordField (Arg2, 0x62, W49B)
CreateDWordField (Arg2, 0x6A, W53B)
CreateDWordField (Arg2, 0x7C, W62B)
CreateDWordField (Arg2, 0x80, W64B)
CreateDWordField (Arg2, 0xB0, W88B)
Store (W49B, W49S)
Store (W53B, W53S)
Store (W62B, W62S)
Store (W64B, W64S)
Store (W88B, W88S)
If (W00B)
{
Or (Local0, 0x8000, Local0)
}
If (LNot (And (W00B, 0x80)))
{
Or (Local0, 0x40, Local0)
}
}
Else
{
Store (0x00, W49S)
Store (0x00, W53S)
Store (0x00, W62S)
Store (0x00, W64S)
Store (0x00, W88S)
}
Store (0x00, A100)
If (And (0x38, W88M))
{
If (And (0x20, W88M))
{
Store (0x08, DMA0)
Or (A100, 0x00100010, A100)
}
Else
{
If (And (0x10, W88M))
{
Store (0x1E, DMA0)
Or (A100, 0x10, A100)
}
Else
{
Store (0x2D, DMA0)
}
}
}
Else
{
If (And (0x07, W88M))
{
Or (0x0100, A100, A100)
If (And (0x04, W88M))
{
Store (0x3C, DMA0)
}
Else
{
If (And (0x02, W88M))
{
Store (0x5A, DMA0)
}
Else
{
Store (0x78, DMA0)
}
}
}
}
If (And (0x3F, W88S))
{
If (And (0x20, W88S))
{
Store (0x08, DMA1)
Or (A100, 0x00200020, A100)
}
Else
{
If (And (0x10, W88S))
{
Store (0x1E, DMA1)
Or (A100, 0x20, A100)
}
Else
{
Store (0x2D, DMA1)
}
}
}
If (LAnd (And (W49M, 0x0800), And (Local4, 0x02)))
{
Or (Local0, 0x02, Local0)
}
If (LLess (PIO0, 0x0384))
{
Or (Local0, 0x01, Local0)
}
If (LAnd (And (W49S, 0x0800), And (Local4, 0x08)))
{
Or (Local0, 0x20, Local0)
}
If (LLess (PIO1, 0x0384))
{
Or (Local0, 0x10, Local0)
}
If (And (Local4, 0x01))
{
Store (PIO0, Local1)
}
Else
{
Store (DMA0, Local1)
}
If (LNot (LLess (Local1, 0xF0)))
{
Or (Local0, 0x08, Local0)
}
Else
{
If (And (W53M, 0x02))
{
If (LAnd (And (W64M, 0x02), LNot (LGreater (Local1, 0x78))))
{
Or (Local0, 0x2301, Local0)
}
Else
{
If (LAnd (And (W64M, 0x01), LNot (LGreater (Local1, 0xB4))))
{
Or (Local0, 0x2101, Local0)
}
}
}
Else
{
Or (Local0, 0x1001, Local0)
}
}
Store (Local0, ITM)
Store (Zero, Local0)
If (And (Local4, 0x04))
{
Store (PIO1, Local1)
}
Else
{
Store (DMA1, Local1)
}
If (And (Local4, 0x10))
{
If (LNot (LLess (Local1, 0xF0)))
{
Or (0x80, ITM, ITM)
}
Else
{
Or (0x10, ITM, ITM)
If (And (W53S, 0x02))
{
If (LAnd (And (W64S, 0x02), LNot (LGreater (Local1, 0x78))))
{
Store (0x0B, Local0)
}
Else
{
If (LAnd (And (W64S, 0x01), LNot (LGreater (Local1, 0xB4))))
{
Store (0x09, Local0)
}
}
}
Else
{
Store (0x04, Local0)
}
}
}
Store (Local0, SIT)
Store (0x00, Local0)
If (LAnd (And (0x3F, W88M), And (Local4, 0x01)))
{
Or (Local0, 0x01, Local0)
}
If (And (Local4, 0x04))
{
Or (Local0, 0x02, Local0)
}
Store (Local0, UDC)
Store (0x00, Local0)
If (And (Local4, 0x01))
{
If (LLess (DMA0, 0x1E))
{
Or (A100, 0x1000, A100)
Or (Local0, 0x01, Local0)
}
Else
{
If (LLess (DMA0, 0x3C))
{
Divide (DMA0, 0x0F, , Local1)
}
Else
{
Divide (DMA0, 0x1E, , Local1)
}
Subtract (0x04, Local1, Local0)
}
}
If (And (Local4, 0x04))
{
If (LLess (DMA1, 0x1E))
{
Or (A100, 0x2000, A100)
Or (Local0, 0x10, Local0)
}
Else
{
If (LLess (DMA1, 0x3C))
{
Divide (DMA1, 0x0F, , Local1)
}
Else
{
Divide (DMA1, 0x1E, , Local1)
}
Subtract (0x04, Local1, Local1)
ShiftLeft (Local1, 0x04, Local1)
Or (Local0, Local1, Local0)
}
}
Store (Local0, UDT)
Store (0x00, Local0)
If (LLess (DMA0, 0x3C))
{
Or (Local0, 0x01, Local0)
}
If (LLess (DMA1, 0x3C))
{
Or (Local0, 0x02, Local0)
}
Store (Local0, ICF)
Return (Local7)
}
Method (GTF0, 7, NotSerialized)
{
Store (Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
}, Local7)
CreateByteField (Local7, 0x01, MODE)
If (And (Arg2, 0x01))
{
If (And (Arg6, 0x01))
{
Store (0x45, MODE)
}
Else
{
And (Arg3, 0x03, Local0)
If (And (Arg4, 0x01))
{
Add (Local0, 0x02, Local0)
}
Or (Local0, 0x40, MODE)
}
}
Else
{
Add (ShiftRight (And (Arg0, 0x0300), 0x08), ShiftRight (And (Arg0, 0x3000), 0x0C), Local0)
If (LNot (LLess (Local0, 0x05)))
{
Store (0x22, MODE)
}
Else
{
If (LNot (LLess (Local0, 0x03)))
{
Store (0x21, MODE)
}
Else
{
Store (0x20, MODE)
}
}
}
Concatenate (Local7, Local7, Local6)
If (LOr (And (Arg0, 0x08), LNot (And (Arg0, 0x01))))
{
If (And (Arg0, 0x02))
{
Store (0x00, MODE)
}
Else
{
Store (0x08, MODE)
}
}
Else
{
Add (ShiftRight (And (Arg0, 0x0300), 0x08), ShiftRight (And (Arg0, 0x3000), 0x0C), Local0)
If (LNot (LLess (Local0, 0x05)))
{
Store (0x0C, MODE)
}
Else
{
If (LNot (LLess (Local0, 0x03)))
{
Store (0x0B, MODE)
}
Else
{
Store (0x0A, MODE)
}
}
}
Concatenate (Local6, Local7, Local5)
Return (Local5)
}
Name (B04, Buffer (0x04) {})
Name (B20, Buffer (0x04) {})
Name (B40, Buffer (0x04) {})
Device (PRIM)
{
Name (_ADR, 0x00)
Name (_PSC, 0x00)
Method (_PS0, 0, NotSerialized)
{
Store (0x00, _PSC)
}
Method (_PS3, 0, NotSerialized)
{
Store (0x03, _PSC)
}
Method (_GTM, 0, NotSerialized)
{
Store (Buffer (0x14)
{
0x00
}, Local0)
Store (^^GTM (^^ITM0, ^^SIT0, ^^UDC0, ^^UDT0, ^^ICF0, ^^FSCB), Local0)
Return (Local0)
}
Method (_STM, 3, NotSerialized)
{
Store (GTF (0x00, Arg1, Arg0), ATA0)
Store (GTF (0x01, Arg2, Arg0), ATA1)
Store (^^STMS (Arg0, Arg1, Arg2), Local0)
CreateDWordField (Local0, 0x00, ITM)
CreateDWordField (Local0, 0x04, SIT)
CreateDWordField (Local0, 0x08, UDC)
CreateDWordField (Local0, 0x0C, UDT)
CreateDWordField (Local0, 0x10, ICF)
Store (ITM, ^^ITM0)
Store (SIT, ^^SIT0)
Store (UDC, ^^UDC0)
Store (UDT, ^^UDT0)
CreateDWordField (Local0, 0x14, A100)
Or (And (^^CB80, 0x0C), ShiftRight (And (0x30, A100), 0x04), ^^CB80)
Or (And (^^FSCB, 0x0C), ShiftRight (And (0x3000, A100), 0x0C), ^^FSCB)
Or (And (^^FATS, 0x0C), ShiftRight (And (0x00300000, A100), 0x14), ^^FATS)
Store (ICF, ^^ICF0)
}
Device (MAST)
{
Name (_ADR, 0x00)
Name (H15F, Zero)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA0))
}
}
}
Device (SECN)
{
Name (_ADR, 0x01)
Name (FAST, 0x63)
Method (_STA, 0, NotSerialized)
{
If (ESID)
{
Return (0x0F)
}
Else
{
Return (0x08)
}
}
Name (_PSC, 0x00)
Method (_PS0, 0, NotSerialized)
{
Store (0x00, _PSC)
}
Method (_PS3, 0, NotSerialized)
{
Store (0x03, _PSC)
}
Method (_GTM, 0, NotSerialized)
{
Store (Buffer (0x14)
{
0x00
}, Local0)
Store (^^FSCB, Local1)
ShiftRight (Local1, 0x02, Local1)
Store (^^GTM (^^ITM1, ^^SIT1, ^^UDC1, ^^UDT1, ^^ICF1, Local1), Local0)
Return (Local0)
}
Method (_STM, 3, NotSerialized)
{
Store (GTF (0x00, Arg1, Arg0), ATA2)
Store (GTF (0x01, Arg2, Arg0), ATA3)
Store (^^STMS (Arg0, Arg1, Arg2), Local0)
CreateDWordField (Local0, 0x00, ITM)
CreateDWordField (Local0, 0x04, SIT)
CreateDWordField (Local0, 0x08, UDC)
CreateDWordField (Local0, 0x0C, UDT)
CreateDWordField (Local0, 0x10, ICF)
Store (ITM, ^^ITM1)
Store (SIT, ^^SIT1)
Store (UDC, ^^UDC1)
Store (UDT, ^^UDT1)
CreateDWordField (Local0, 0x14, A100)
Or (And (^^CB80, 0x03), ShiftRight (And (0x30, A100), 0x02), ^^CB80)
Or (And (^^FSCB, 0x03), ShiftRight (And (0x3000, A100), 0x0A), ^^FSCB)
Or (And (^^FATS, 0x03), ShiftRight (And (0x00300000, A100), 0x12), ^^FATS)
Store (ICF, ^^ICF1)
}
Device (BAY1)
{
Name (_ADR, 0x00)
Name (H15F, Zero)
Name (EJ0F, 0x00)
Method (_GTF, 0, NotSerialized)
{
Return (RATA (ATA2))
}
Method (_STA, 0, NotSerialized)
{
If (\_SB.PCI0.IDE0.ESID)
{
\_SB.PCI0.IDE0.SECN.CBAY ()
Store (^^BFLG, Local0)
If (LEqual (^^BNUM, 0x01))
{
If (And (Local0, 0x01))
{
If (\_SB.PCI0.LPC0.LV37)
{
Return (0x08)
}
Else
{
Return (0x0F)
}
}
}
Else
{
If (LEqual (^^BNUM, 0x02))
{
If (\_SB.PCI0.LPC0.LV37)
{
Return (0x08)
}
Else
{
Return (0x0F)
}
}
Else
{
Return (0x08)
}
}
}
Else
{
Return (0x08)
}
}
Method (_EJ0, 1, NotSerialized)
{
If (Arg0)
{
Store (0x01, ^^^SSIG)
Sleep (0x32)
Store (0xC000, ^^^ITM1)
Store (0x01, \_SB.PCI0.LPC0.LV37)
Store (0x00, \_SB.PCI0.LPC0.LV39)
}
}
}
Name (BNUM, 0x00)
Name (BFLG, 0x00)
Method (CBAY, 0, NotSerialized)
{
Store (0x00, BNUM)
Store (0x00, BFLG)
Store (\_SB.PCI0.LPC0.RBID, Local0)
If (Or (LEqual (Local0, 0x01), LEqual (Local0, 0x02)))
{
Increment (BNUM)
Or (BFLG, 0x01, BFLG)
}
}
}
Method (_PS0, 0, NotSerialized)
{
If (And (LEqual (_PSC, 0x03), LEqual (\_SB.STAT, 0x03)))
{
Store (0x89, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
Store (0x00, _PSC)
}
Method (_PS3, 0, NotSerialized)
{
Store (0x03, _PSC)
}
Name (_PSC, 0x00)
}
Device (USB1)
{
Name (_ADR, 0x001D0000)
OperationRegion (USBO, PCI_Config, 0xC4, 0x04)
Field (USBO, ByteAcc, NoLock, Preserve)
{
RSEN, 2
}
Name (_PRW, Package (0x02)
{
0x03,
0x03
})
Method (_PSW, 1, NotSerialized)
{
If (Arg0)
{
Store (0x03, \_SB.PCI0.USB1.RSEN)
}
Else
{
Store (0x00, \_SB.PCI0.USB1.RSEN)
}
}
}
Device (USB2)
{
Name (_ADR, 0x001D0001)
OperationRegion (USBO, PCI_Config, 0xC4, 0x04)
Field (USBO, ByteAcc, NoLock, Preserve)
{
RSEN, 2
}
Name (_PRW, Package (0x02)
{
0x04,
0x03
})
Method (_PSW, 1, NotSerialized)
{
If (Arg0)
{
Store (0x03, \_SB.PCI0.USB2.RSEN)
}
Else
{
Store (0x00, \_SB.PCI0.USB2.RSEN)
}
}
}
Device (USB3)
{
Name (_ADR, 0x001D0002)
OperationRegion (USBO, PCI_Config, 0xC4, 0x04)
Field (USBO, ByteAcc, NoLock, Preserve)
{
RSEN, 2
}
Name (_PRW, Package (0x02)
{
0x0C,
0x03
})
Method (_PSW, 1, NotSerialized)
{
If (Arg0)
{
Store (0x03, \_SB.PCI0.USB3.RSEN)
}
Else
{
Store (0x00, \_SB.PCI0.USB3.RSEN)
}
}
}
}
Device (LID)
{
Name (_HID, EisaId ("PNP0C0D"))
Name (LSTS, 0x00)
Method (_LID, 0, NotSerialized)
{
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.LIDS)
{
Store (Zero, LSTS)
}
Else
{
Store (One, LSTS)
}
}
Else
{
Store (Zero, LSTS)
}
Return (LSTS)
}
}
Device (ACAD)
{
Name (_HID, "ACPI0003")
Name (_PCL, Package (0x01)
{
\_SB
})
Name (ACWT, 0x00)
Method (_PSR, 0, NotSerialized)
{
Store (\_SB.ACST, ACWT)
If (\_SB.OKEC)
{
Store (\_SB.PCI0.LPC0.EC0.ACDF, \_SB.ACST)
}
If (LNot (LEqual (ACWT, \_SB.ACST)))
{
Store (0x8B, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
Return (\_SB.ACST)
}
}
Method (VTOB, 1, NotSerialized)
{
Store (0x01, Local0)
ShiftLeft (Local0, Arg0, Local0)
Return (Local0)
}
Method (BTOV, 1, NotSerialized)
{
ShiftRight (Arg0, 0x01, Local0)
Store (0x00, Local1)
While (Local0)
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
Return (Local1)
}
Method (MKWD, 2, NotSerialized)
{
If (And (Arg1, 0x80))
{
Store (0xFFFF0000, Local0)
}
Else
{
Store (Zero, Local0)
}
Or (Local0, Arg0, Local0)
Or (Local0, ShiftLeft (Arg1, 0x08), Local0)
Return (Local0)
}
Method (POSW, 1, NotSerialized)
{
If (And (Arg0, 0x8000))
{
If (LEqual (Arg0, 0xFFFF))
{
Return (0xFFFFFFFF)
}
Else
{
Not (Arg0, Local0)
Increment (Local0)
And (Local0, 0xFFFF, Local0)
Return (Local0)
}
}
Else
{
Return (Arg0)
}
}
Method (GBFE, 3, NotSerialized)
{
CreateByteField (Arg0, Arg1, TIDX)
Store (TIDX, Arg2)
}
Method (PBFE, 3, NotSerialized)
{
CreateByteField (Arg0, Arg1, TIDX)
Store (Arg2, TIDX)
}
Method (ITOS, 1, NotSerialized)
{
Store (Buffer (0x09)
{
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
}, Local0)
Store (Buffer (0x11)
{
"0123456789ABCDEF"
}, Local7)
Store (0x08, Local1)
Store (0x00, Local2)
Store (0x00, Local3)
While (Local1)
{
Decrement (Local1)
And (ShiftRight (Arg0, ShiftLeft (Local1, 0x02)), 0x0F, Local4)
If (Local4)
{
Store (Ones, Local3)
}
If (Local3)
{
GBFE (Local7, Local4, RefOf (Local5))
PBFE (Local0, Local2, Local5)
Increment (Local2)
}
}
Return (Local0)
}
Device (BAT1)
{
Name (_HID, EisaId ("PNP0C0A"))
Name (_UID, 0x01)
Name (_PCL, Package (0x01)
{
\_SB
})
Name (PBIF, Package (0x0D)
{
0x01,
0xFFFFFFFF,
0xFFFFFFFF,
0x01,
0xFFFFFFFF,
0xFA,
0x64,
0x0A,
0x19,
"BAT1",
" ",
" ",
" "
})
Name (PBST, Package (0x04)
{
0x00,
0xFFFFFFFF,
0xFFFFFFFF,
0x2710
})
Name (BAST, 0x00)
Name (FAST, 0x00)
Name (B1ST, 0x0F)
Name (B1WT, 0x00)
Method (_STA, 0, NotSerialized)
{
If (LLess (FAST, 0x10))
{
Increment (FAST)
If (LEqual (FAST, 0x10))
{
Store (0x92, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
}
}
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.MBTS)
{
Store (0x1F, B1ST)
}
Else
{
Store (0x0F, B1ST)
}
}
Else
{
Store (0x0F, B1ST)
}
Return (B1ST)
}
Method (_BIF, 0, NotSerialized)
{
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.MBTS)
{
UPBI ()
}
Else
{
IVBI ()
}
}
Else
{
IVBI ()
}
Return (PBIF)
}
Method (_BST, 0, NotSerialized)
{
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.MBTS)
{
UPBS ()
}
Else
{
IVBS ()
}
}
Else
{
IVBS ()
}
Return (PBST)
}
Method (UPBI, 0, NotSerialized)
{
Store (0x1FFF, Local2)
\_SB.PCI0.LPC0.EC0.SMWR (0x08, 0x14, 0x01, Local2)
\_SB.PCI0.LPC0.EC0.SMRD (0x09, 0x14, 0x01, RefOf (Local3))
If (LEqual (Local2, Or (Local3, 0x0FFF)))
{
If (LNot (\_SB.PCI0.LPC0.EC0.SMRD (0x09, 0x16, 0x10, RefOf (Local5))))
{
Store (Local5, Index (PBIF, 0x02))
}
}
If (LEqual (\_SB.PCI0.LPC0.EC0.MBID, 0x01))
{
Store (0x1130, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("01ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SMP ", Index (PBIF, 0x0C))
}
Else
{
If (LEqual (\_SB.PCI0.LPC0.EC0.MBID, 0x02))
{
Store (0x0E10, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("02ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SANYO", Index (PBIF, 0x0C))
}
Else
{
If (LEqual (\_SB.PCI0.LPC0.EC0.MBID, 0x03))
{
Store (0x1130, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("03ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SANYO", Index (PBIF, 0x0C))
}
Else
{
Store (0x1130, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("01ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SMP ", Index (PBIF, 0x0C))
}
}
}
Store (0x01, Index (PBIF, 0x00))
If (LEqual (SizeOf (\_OS), 0x27))
{
Store (0x00, Index (PBIF, 0x00))
}
}
Method (UPBS, 0, NotSerialized)
{
Store (\_SB.PCI0.LPC0.EC0.MCUR, Local5)
Store (POSW (Local5), Index (PBST, 0x01))
Store (\_SB.PCI0.LPC0.EC0.MBRM, Index (PBST, 0x02))
Store (\_SB.PCI0.LPC0.EC0.MBVG, Index (PBST, 0x03))
If (\_SB.PCI0.LPC0.EC0.MBTF)
{
If (\_SB.PCI0.LPC0.EC0.ACDF)
{
Store (0x00, Index (PBST, 0x00))
}
}
Else
{
If (\_SB.PCI0.LPC0.EC0.MBTC)
{
If (\_SB.PCI0.LPC0.EC0.ACDF)
{
Store (0x02, Index (PBST, 0x00))
}
Else
{
Store (0x00, Index (PBST, 0x00))
}
}
Else
{
If (\_SB.PCI0.LPC0.EC0.ACDF)
{
Store (0x00, Index (PBST, 0x00))
}
Else
{
Store (0x01, Index (PBST, 0x00))
}
}
}
}
Method (IVBI, 0, NotSerialized)
{
Store (0xFFFFFFFF, Index (PBIF, 0x01))
Store (0xFFFFFFFF, Index (PBIF, 0x02))
Store (0xFFFFFFFF, Index (PBIF, 0x04))
Store ("Bad", Index (PBIF, 0x09))
Store (" ", Index (PBIF, 0x0A))
Store ("Bad", Index (PBIF, 0x0B))
Store ("Bad", Index (PBIF, 0x0C))
}
Method (IVBS, 0, NotSerialized)
{
Store (0x00, Index (PBST, 0x00))
Store (0xFFFFFFFF, Index (PBST, 0x01))
Store (0xFFFFFFFF, Index (PBST, 0x02))
Store (0x2710, Index (PBST, 0x03))
}
}
Device (BAT2)
{
Name (_HID, EisaId ("PNP0C0A"))
Name (_UID, 0x02)
Name (_PCL, Package (0x01)
{
\_SB
})
Name (B2ST, 0x0F)
Name (PBIF, Package (0x0D)
{
0x01,
0xFFFFFFFF,
0xFFFFFFFF,
0x01,
0xFFFFFFFF,
0xFA,
0x64,
0x0A,
0x19,
"BAT1",
" ",
" ",
" "
})
Name (PBST, Package (0x04)
{
0x00,
0xFFFFFFFF,
0xFFFFFFFF,
0x2710
})
Method (_STA, 0, NotSerialized)
{
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.SBTS)
{
Store (0x1F, B2ST)
}
Else
{
Store (0x0F, B2ST)
}
}
Else
{
Store (0x0F, B2ST)
}
Return (B2ST)
}
Method (_BIF, 0, NotSerialized)
{
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.SBTS)
{
UPBI ()
}
Else
{
IVBI ()
}
}
Else
{
IVBI ()
}
Return (PBIF)
}
Method (_BST, 0, NotSerialized)
{
If (\_SB.OKEC)
{
If (\_SB.PCI0.LPC0.EC0.SBTS)
{
UPBS ()
}
Else
{
IVBS ()
}
}
Else
{
IVBS ()
}
Return (PBST)
}
Method (UPBI, 0, NotSerialized)
{
Store (0x2FFF, Local2)
\_SB.PCI0.LPC0.EC0.SMWR (0x08, 0x14, 0x01, Local2)
\_SB.PCI0.LPC0.EC0.SMRD (0x09, 0x14, 0x01, RefOf (Local3))
If (LEqual (Local2, Or (Local3, 0x0FFF)))
{
If (LNot (\_SB.PCI0.LPC0.EC0.SMRD (0x09, 0x16, 0x10, RefOf (Local5))))
{
Store (Local5, Index (PBIF, 0x02))
}
}
If (LEqual (\_SB.PCI0.LPC0.EC0.SBID, 0x01))
{
Store (0x1130, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("01ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SMP ", Index (PBIF, 0x0C))
}
Else
{
If (LEqual (\_SB.PCI0.LPC0.EC0.SBID, 0x02))
{
Store (0x0E10, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("02ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SANYO", Index (PBIF, 0x0C))
}
Else
{
If (LEqual (\_SB.PCI0.LPC0.EC0.SBID, 0x03))
{
Store (0x1130, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("03ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SANYO", Index (PBIF, 0x0C))
}
Else
{
Store (0x0E10, Index (PBIF, 0x01))
Store (0x39D0, Index (PBIF, 0x04))
Store ("02ZG", Index (PBIF, 0x09))
Store ("LION", Index (PBIF, 0x0B))
Store ("SANYO", Index (PBIF, 0x0C))
}
}
}
Store (0x01, Index (PBIF, 0x00))
If (LEqual (SizeOf (\_OS), 0x27))
{
Store (0x00, Index (PBIF, 0x00))
}
}
Method (UPBS, 0, NotSerialized)
{
Store (\_SB.PCI0.LPC0.EC0.ACUR, Local5)
Store (POSW (Local5), Index (PBST, 0x01))
Store (\_SB.PCI0.LPC0.EC0.ABRM, Index (PBST, 0x02))
Store (\_SB.PCI0.LPC0.EC0.ABVG, Index (PBST, 0x03))
If (\_SB.PCI0.LPC0.EC0.SBTF)
{
If (\_SB.PCI0.LPC0.EC0.ACDF)
{
Store (0x00, Index (PBST, 0x00))
}
}
Else
{
If (\_SB.PCI0.LPC0.EC0.SBTC)
{
If (\_SB.PCI0.LPC0.EC0.ACDF)
{
Store (0x02, Index (PBST, 0x00))
}
Else
{
Store (0x00, Index (PBST, 0x00))
}
}
Else
{
If (\_SB.PCI0.LPC0.EC0.ACDF)
{
Store (0x00, Index (PBST, 0x00))
}
Else
{
Store (0x01, Index (PBST, 0x00))
}
}
}
}
Method (IVBI, 0, NotSerialized)
{
Store (0xFFFFFFFF, Index (PBIF, 0x01))
Store (0xFFFFFFFF, Index (PBIF, 0x02))
Store (0xFFFFFFFF, Index (PBIF, 0x04))
Store ("Bad", Index (PBIF, 0x09))
Store (" ", Index (PBIF, 0x0A))
Store ("Bad", Index (PBIF, 0x0B))
Store ("Bad", Index (PBIF, 0x0C))
}
Method (IVBS, 0, NotSerialized)
{
Store (0x00, Index (PBST, 0x00))
Store (0xFFFFFFFF, Index (PBST, 0x01))
Store (0xFFFFFFFF, Index (PBST, 0x02))
Store (0x2710, Index (PBST, 0x03))
}
}
Scope (\_TZ)
{
Name (TPL, 0x0CA0)
Name (TAC1, 0x0D0E)
Name (TAC0, 0x0D54)
Name (TPAS, 0x0E44)
Name (TPC, 0x0E94)
Name (TPTM, 0x0C3C)
Name (TBSE, 0x0AAC)
Name (LTMP, 0x0CA0)
Name (TVAR, Buffer (0x05)
{
0x00, 0x20, 0x1F, 0x0C, 0x1F
})
CreateByteField (TVAR, 0x00, PLCY)
CreateWordField (TVAR, 0x01, CTOS)
CreateWordField (TVAR, 0x03, CTHY)
Device (FAN0)
{
Name (_HID, EisaId ("PNP0C0B"))
Name (_UID, 0x01)
Name (_PR0, Package (0x01)
{
PFN0
})
Method (_PS0, 0, NotSerialized)
{
Store ("Low Speed FAN - _PS0", Debug)
}
Method (_PS3, 0, NotSerialized)
{
Store ("Low Speed FAN - _PS3", Debug)
}
}
PowerResource (PFN0, 0x00, 0x0000)
{
Name (FNS1, 0x00)
Name (FFST, 0x01)
Method (_STA, 0, NotSerialized)
{
Store (FNS1, Local1)
Return (Local1)
}
Method (_ON, 0, NotSerialized)
{
Store (0x01, FNS1)
If (\_TZ.PFN1.FNS2)
{
Store ("FAN 1 (High speed already turn on) ", Debug)
}
Else
{
If (\_SB.OKEC)
{
Store (0xB4, \_SB.PCI0.LPC0.EC0.FSPD)
Store (0x01, \_SB.PCI0.LPC0.EC0.FPR1)
}
}
If (Or (LEqual (\_SB.PCI0.MYOS, 0x01), LEqual (\_SB.PCI0.MYOS, 0x03)))
{
\_TZ.THRM._SCP (0x01)
}
}
Method (_OFF, 0, NotSerialized)
{
Store (0x00, FNS1)
If (LEqual (SizeOf (\_OS), 0x14))
{
If (\_SB.OKEC)
{
If (\_TZ.PFN1.FNS2)
{
Store (One, \_SB.PCI0.LPC0.EC0.FPR1)
}
Else
{
Store (Zero, \_SB.PCI0.LPC0.EC0.FPR1)
}
}
}
Else
{
If (LLess (FFST, 0x02))
{
Store (0x86, \_SB.PCI0.LPC0.BCMD)
Store (0x00, \_SB.PCI0.LPC0.SMIC)
Increment (FFST)
}
Else
{
If (\_SB.OKEC)
{
Store (0x00, \_SB.PCI0.LPC0.EC0.FPR1)
}
}
}
If (Or (LEqual (\_SB.PCI0.MYOS, 0x01), LEqual (\_SB.PCI0.MYOS, 0x03)))
{
\_TZ.THRM._SCP (0x01)
}
}
}
Device (FAN1)
{
Name (_HID, EisaId ("PNP0C0B"))
Name (_UID, 0x02)
Name (_PR0, Package (0x02)
{
PFN0,
PFN1
})
Method (_PS0, 0, NotSerialized)
{
Store ("High Speed FAN - _PS0", Debug)
}
Method (_PS3, 0, NotSerialized)
{
Store ("High Speed FAN - _PS3", Debug)
}
}
PowerResource (PFN1, 0x00, 0x0000)
{
Name (FNS2, 0x00)
Method (_STA, 0, NotSerialized)
{
Return (FNS2)
}
Method (_ON, 0, NotSerialized)
{
Store (0x01, FNS2)
If (\_SB.OKEC)
{
Store (0xFF, \_SB.PCI0.LPC0.EC0.FSPD)
Store (0x01, \_SB.PCI0.LPC0.EC0.FPR1)
}
If (Or (LEqual (\_SB.PCI0.MYOS, 0x01), LEqual (\_SB.PCI0.MYOS, 0x03)))
{
\_TZ.THRM._SCP (0x01)
}
}
Method (_OFF, 0, NotSerialized)
{
Store (Zero, FNS2)
Store (0x00, FNS2)
If (\_TZ.PFN0.FNS1)
{
If (\_SB.OKEC)
{
Store (0xB4, \_SB.PCI0.LPC0.EC0.FSPD)
Store (0x01, \_SB.PCI0.LPC0.EC0.FPR1)
}
}
Else
{
If (\_SB.OKEC)
{
Store (0x00, \_SB.PCI0.LPC0.EC0.FPR1)
}
}
If (Or (LEqual (\_SB.PCI0.MYOS, 0x01), LEqual (\_SB.PCI0.MYOS, 0x03)))
{
\_TZ.THRM._SCP (0x01)
}
}
}
ThermalZone (THRM)
{
Name (_AL0, Package (0x01)
{
FAN1
})
Method (_AC0, 0, NotSerialized)
{
Return (TAC0)
}
Name (_AL1, Package (0x01)
{
FAN0
})
Method (_AC1, 0, NotSerialized)
{
Return (TAC1)
}
Method (_CRT, 0, NotSerialized)
{
Return (TPC)
}
Method (_PSV, 0, NotSerialized)
{
Return (TPAS)
}
Name (_TSP, 0x64)
Method (_TMP, 0, NotSerialized)
{
If (\_SB.OKEC)
{
Store (\_SB.PCI0.LPC0.EC0.CTMP, Local1)
Store ("Current Temperature is ----------- ", Debug)
Store (Local1, Debug)
Store (Local1, \_SB.CM25)
Add (Multiply (Local1, 0x0A), TBSE, Local1)
}
Else
{
Store (LTMP, Local1)
}
Return (Local1)
}
Name (_PSL, Package (0x01)
{
\_PR.CPU0
})
Name (_TC1, 0x02)
Name (_TC2, 0x03)
Method (_SCP, 1, NotSerialized)
{
Store (Zero, PLCY)
If (\_TZ.PFN0.FNS1)
{
If (LEqual (\_TZ.PFN1.FNS2, 0x00))
{
Store (0x0D22, TAC1)
Store (0x0D86, TAC0)
}
Else
{
Store (0x0D22, TAC1)
Store (0x0D40, TAC0)
}
}
Else
{
If (\_TZ.PFN1.FNS2)
{
Store (0x0D22, TAC1)
Store (0x0D40, TAC0)
}
Else
{
Store (0x0D40, TAC1)
Store (0x0D86, TAC0)
}
}
Store (0x0E44, TPAS)
Notify (\_TZ.THRM, 0x81)
}
}
}
Device (SLPB)
{
Name (_HID, EisaId ("PNP0C0E"))
}
OperationRegion (EXCO, SystemIO, 0x72, 0x02)
Field (EXCO, ByteAcc, NoLock, Preserve)
{
INDX, 8,
DATA, 8
}
IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)
{
Offset (0x20),
ACST, 1,
OKEC, 1,
POPF, 1,
BLTF, 1,
W2KF, 2,
S4WP, 1,
FLA7, 1,
LSFG, 1,
LD10, 1,
PS2M, 1,
DISD, 3,
OVRL, 1,
Offset (0x22),
SLEE, 8,
BPFG, 8,
PWST, 8,
CM25, 8,
CM26, 8,
CM27, 8,
CM28, 16,
CM2A, 16,
F4FG, 1,
Offset (0x30),
CM30, 8,
CM31, 8,
CM32, 8
}
}
}
[-- Attachment #4: boot-radeon.c --]
[-- Type: text/x-csrc, Size: 821 bytes --]
#define LRMI_DEBUG 1
#include <stdlib.h>
#include <stdio.h>
#include <lrmi.h>
void err(char *function, int exitval) {
fprintf(stderr, "%s():\n");
exit(exitval);
}
int main () {
struct LRMI_regs regs;
ioperm(0, 1024, 1);
iopl(3);
if (!LRMI_init()) {
err("LRMI_init", 1);
}
memset(®s, 0, sizeof(regs));
/*
if ((pvp = xf86GetPciInfoForEntity(pInt->entityIndex)))
X86_AX = (pvp->bus << 8) | (pvp->device << 3) | (pvp->func & 0x7);
pushw(pInt, X86_CS);
pushw(pInt, X86_IP);
X86_CS = pInt->BIOSseg;
X86_EIP = 0x0003;
X86_ES = 0; // standard pc es
*/
regs.eax = ((1 << 8) | (0 << 3) | (0 & 0x7)) & 0x0000FFFF;
regs.cs = 0x0000c000;
regs.ip = 0x00000003;
//regs.ip = 0;
//regs.es = 0;
if (!LRMI_call(®s)) {
err("LRMI_int", -1);
}
exit(0);
}
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
2004-08-04 14:52 ` Len Brown
2004-08-04 17:44 ` count0-tC47gz4GrgtWk0Htik3J/w
@ 2004-08-06 6:13 ` ole.rohne-vJEk5272eHo
[not found] ` <yzosmb0hjzu.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
1 sibling, 1 reply; 54+ messages in thread
From: ole.rohne-vJEk5272eHo @ 2004-08-06 6:13 UTC (permalink / raw)
To: Len Brown; +Cc: Acpi Devel, Erik Tews, Nathan Bryant, Andrew Barr
Len> I would like a solution that applies to x86_64 in addition to
Len> i386.
What would it take?
I know absolutely nothing about that architecture. From
arch/x86_64/kernel/acpi/wakeup.S it seems to support some form of real
mode, so could it do the return to real mode just like i386?
Len> Can you summarize the feedback you've got so far?
Failures and success:
=====================
One failure report (Stefan), that's the Radeon 7000 failure you're
referring to. It's an AGP system, I'm anxious to know if adding the
bus number helps.
Two success reports, both with Dell d660/Radeon 9000.
My own machine is a Fujitsu P2120/Radeon Mobility M6 LY.
Len> Can you re-post the cleaned up patch?
It's on my todo list:-)
Len> Maybe good to go to lkml with it for broader review and feedback.
"lkml" - is that the linux kernel mailing list? I'm not a seasoned
kernel patch provider.
Ole
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* Re: Radeon PM Support
[not found] ` <88056F38E9E48644A0F562A38C64FB600289AE7C-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
@ 2004-08-06 6:29 ` ole.rohne-vJEk5272eHo
[not found] ` <e796392204080601016e29a349@mail.gmail.com>
2004-08-06 15:03 ` Alexander Bruder
2004-08-11 17:32 ` Matthew Garrett
2 siblings, 1 reply; 54+ messages in thread
From: ole.rohne-vJEk5272eHo @ 2004-08-06 6:29 UTC (permalink / raw)
To: Pallipadi, Venkatesh
Cc: anib-La3J9u0raUk, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
Venki> Does this addon patch (over the Ole's original patch) help?
I've been hesitant to propose a generic VGAPOST, but it could be good
to have a way of resuming without using a driver. Would it be cleaner
to put the call in pci_default_resume?
Venki> This works with Radeon 9000M and frame buffer for me.
Is that "frame buffer" as in aty/radeonfb? Then I'd expect the resume
code in aty/radeon_pm gets to run instead of your generic resume?
Ole
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* Re: Radeon PM Support
[not found] ` <yzo4qngh7ji.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
@ 2004-08-06 12:32 ` Stefan Schweizer
[not found] ` <e796392204080605327588e5ac-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2004-08-12 14:30 ` Stefan Schweizer
1 sibling, 1 reply; 54+ messages in thread
From: Stefan Schweizer @ 2004-08-06 12:32 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo@public.gmane.org,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
On 06 Aug 2004 12:42:25 +0200, ole.rohne |at| cern.ch <ole.rohne at
cern.ch> wrote:
> Please, what it your system?
Acer Aspire 1406LC, radeon mobility m6, intel agp bridge
> I've had another report like that but I don't see it on my system
> (P2120). It looks like some resume driver is stuck waiting for an
> interrupt, it's not necessarily connected to the graphics.
But it works when I do not apply your patch and no fb and use Xorg to
get the screen back.
>
> Schweizer> It still is no solution for the intel-agp not working for me.
>
> My system is PCI only so I don't know anything about AGP. However, it
> seems that agp_intel_resume writes a bunch of default values to the
> pci config space, is it possible that XFree plays directly with those
> and expect them to stay across suspend/resume?
>
> Ole
>
how can I avoid this?
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* Re: Radeon PM Support
[not found] ` <e796392204080605327588e5ac-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2004-08-06 13:38 ` Nathan Bryant
0 siblings, 0 replies; 54+ messages in thread
From: Nathan Bryant @ 2004-08-06 13:38 UTC (permalink / raw)
To: Stefan Schweizer
Cc: ole.rohne-vJEk5272eHo@public.gmane.org,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Stefan Schweizer wrote:
>On 06 Aug 2004 12:42:25 +0200, ole.rohne |at| cern.ch <ole.rohne at
>cern.ch> wrote:
>
>
>>Please, what it your system?
>>
>>
>
>Acer Aspire 1406LC, radeon mobility m6, intel agp bridge
>
>
>
>>I've had another report like that but I don't see it on my system
>>(P2120). It looks like some resume driver is stuck waiting for an
>>interrupt, it's not necessarily connected to the graphics.
>>
>>
>
>But it works when I do not apply your patch and no fb and use Xorg to
>get the screen back.
>
>
>>Schweizer> It still is no solution for the intel-agp not working for me.
>>
>>My system is PCI only so I don't know anything about AGP. However, it
>>seems that agp_intel_resume writes a bunch of default values to the
>>pci config space, is it possible that XFree plays directly with those
>>and expect them to stay across suspend/resume?
>>
nvidia has their own NvAGP that is supposed to handle AGP save/restore
better. Unfortunately, the driver as a whole oopses on suspend and
they're not sharing it ;)
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* Re: Radeon PM Support
[not found] ` <yzosmb0hjzu.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
@ 2004-08-06 13:39 ` Nathan Bryant
[not found] ` <41138A16.5000908-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
2004-08-06 13:58 ` Andi Kleen
2004-08-11 19:39 ` Pavel Machek
2 siblings, 1 reply; 54+ messages in thread
From: Nathan Bryant @ 2004-08-06 13:39 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo; +Cc: Len Brown, Acpi Devel, Erik Tews, Andrew Barr
ole.rohne-vJEk5272eHo@public.gmane.org wrote:
>Len> I would like a solution that applies to x86_64 in addition to
>Len> i386.
>
>What would it take?
>
>I know absolutely nothing about that architecture. From
>arch/x86_64/kernel/acpi/wakeup.S it seems to support some form of real
>mode, so could it do the return to real mode just like i386?
>
>Len> Can you summarize the feedback you've got so far?
>
>Failures and success:
>=====================
>One failure report (Stefan), that's the Radeon 7000 failure you're
>referring to. It's an AGP system, I'm anxious to know if adding the
>bus number helps.
>
>
Maybe we need proper AGP save/restore before we can POST?
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* Re: Radeon PM Support
[not found] ` <yzosmb0hjzu.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
2004-08-06 13:39 ` Nathan Bryant
@ 2004-08-06 13:58 ` Andi Kleen
2004-08-11 19:39 ` Pavel Machek
2 siblings, 0 replies; 54+ messages in thread
From: Andi Kleen @ 2004-08-06 13:58 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo
Cc: Len Brown, Acpi Devel, Erik Tews, Nathan Bryant, Andrew Barr
On Fri, Aug 06, 2004 at 08:13:25AM +0200, ole.rohne-vJEk5272eHo@public.gmane.org wrote:
> Len> I would like a solution that applies to x86_64 in addition to
> Len> i386.
>
> What would it take?
>
> I know absolutely nothing about that architecture. From
> arch/x86_64/kernel/acpi/wakeup.S it seems to support some form of real
> mode, so could it do the return to real mode just like i386?
x86-64 S3 wakeups works exactly the same as i386, it just switches
to long mode instead of 32bit mode. x86-64 has real mode too
(it is a fully compatible PC with an additional 64bit long mode)
The code is slightly different for historical reasons, but
if you have real mode POST code you can probably just insert
it into the real mode part of the x86-64 S3 wakeup.
-Andi
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* Re: Radeon PM Support
[not found] ` <41138A16.5000908-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
@ 2004-08-06 14:05 ` ole.rohne-vJEk5272eHo
[not found] ` <yzo7jscnyyu.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: ole.rohne-vJEk5272eHo @ 2004-08-06 14:05 UTC (permalink / raw)
To: Nathan Bryant, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Ole> One failure report (Stefan), that's the Radeon 7000 failure you're
Ole> referring to. It's an AGP system,
It is actually a Radeon 9000, however AGP
Nathan> Maybe we need proper AGP save/restore before we can POST?
I'd strongly suspect so, I was stupidly assuming it was there
already...
This could be a possible explanation for the problems that the two
Stefans are seeing: POSTing with XFree86 works because XFree86 does
the AGP restoration.
Ole
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* Re: Radeon PM Support
[not found] ` <88056F38E9E48644A0F562A38C64FB600289AE7C-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2004-08-06 6:29 ` ole.rohne-vJEk5272eHo
@ 2004-08-06 15:03 ` Alexander Bruder
2004-08-11 17:32 ` Matthew Garrett
2 siblings, 0 replies; 54+ messages in thread
From: Alexander Bruder @ 2004-08-06 15:03 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Hi,
> Does this addon patch (over the Ole's original patch) help?
>
> This works with Radeon 9000M and frame buffer for me. This
> should also help any other graphics drivers which doesn't
> implement their own suspend resume functions.
no it doesn't work. I tried with and without fb, disabled X, unloaded all
modules but the video card never came back.
Alexander
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* RE: Radeon PM Support
@ 2004-08-06 16:35 Pallipadi, Venkatesh
[not found] ` <88056F38E9E48644A0F562A38C64FB60028F9AC3-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Pallipadi, Venkatesh @ 2004-08-06 16:35 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo, Nathan Bryant,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, anib-La3J9u0raUk
>-----Original Message-----
>From: acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
>[mailto:acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org] On Behalf Of
>ole.rohne-vJEk5272eHo@public.gmane.org
> Venki> Does this addon patch (over the Ole"s original patch) help?
>
> I"ve been hesitant to propose a generic VGAPOST, but it could be good
> to have a way of resuming without using a driver. Would it be cleaner
> to put the call in pci_default_resume?
Yes. If this patch works for tohers, then we can move it into
pci_default_resume during the cleanup.
>
> Venki> This works with Radeon 9000M and frame buffer for me.
>
> Is that "frame buffer" as in aty/radeonfb? Then I"d expect the resume
> code in aty/radeon_pm gets to run instead of your generic resume?
No. I meant VESA frame buffer. And it also works w/o framebuffer
(std VGA).
I am still wondering why it doesn't work for Alexander.
Alexander: Is your card sitting on PCI or AGP?
Thanks,
Venki
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* Re: Radeon PM Support
[not found] ` <yzo7jscnyyu.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
@ 2004-08-06 19:09 ` Stefan Dösinger
2004-08-08 14:53 ` Stefan Schweizer
1 sibling, 0 replies; 54+ messages in thread
From: Stefan Dösinger @ 2004-08-06 19:09 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: ole.rohne-vJEk5272eHo, Nathan Bryant
> This could be a possible explanation for the problems that the two
> Stefans are seeing: POSTing with XFree86 works because XFree86 does
> the AGP restoration.
Remember that posting from kernel crashes without prior suspend and posting
from console with lrmi works without X11.
Not loading intel-agp makes no difference(kernel mode crash, user mode works)
Stefan Dösinger
(tm803)
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* Re: Radeon PM Support
[not found] ` <200408051914.39445.anib-La3J9u0raUk@public.gmane.org>
2004-08-05 19:53 ` Stefan Dösinger
@ 2004-08-06 20:03 ` Ow Mun Heng
1 sibling, 0 replies; 54+ messages in thread
From: Ow Mun Heng @ 2004-08-06 20:03 UTC (permalink / raw)
To: Acpi-List
On Thu, 2004-08-05 at 10:14, Alexander Bruder wrote:
> Hi,
>
> > Intel's new graphics chipset probably. Owners of Acer Travelmate 60X told
> > me that the video doesn't come back. But in the these case the whole system
> > locked up on resume, so we can't tell if the video resume works.
>
> it also happends for the 80x series (in my case 801Lcib) with ATI Technologies
> Inc Radeon R250 Lf [Radeon Mobility 9000] using the framebuffer.
> "echo 3 > /proc/acpi/sleep" and "echo 4 > /proc/acpi/sleep" doesn't work
echo 4 works on My D600 Radeon 9000. S3 doesn't. FC2 on 2.6.7 kernel
--
Ow Mun Heng
Fedora GNU/Linux Core 2 on D600 1.4Ghz CPU kernel
2.6.7-2.jul1-interactive
Neuromancer 13:01:00 up 4:19, 5 users, load average: 2.28, 1.93, 2.64
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* Re: Radeon PM Support
[not found] ` <20040730141028.GE21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
2004-07-30 13:31 ` Andrew Barr
2004-07-30 14:27 ` wwp
@ 2004-08-06 20:10 ` Ow Mun Heng
2 siblings, 0 replies; 54+ messages in thread
From: Ow Mun Heng @ 2004-08-06 20:10 UTC (permalink / raw)
To: Acpi-List
On Fri, 2004-07-30 at 07:10, Micha Feigin wrote:
> On Thu, Jul 29, 2004 at 10:14:00PM +0000, Andrew Barr wrote:
> > I just bought a Radeon 7000 video card on-line. What is the status of
> > and plans for power management support for this card? I read
>
> I am not sure about the current state of things. AFAIK the problem was
> with dri suspend support for radeon, and at the time at least, the card
> was reset on VT switch to enable suspend. IIRC the patch was
> incorporated into main the main tree quite some time ago.
I think this problem must be 2fold.
1. The Bios implementation
2. the X server
Why? Cause by experience on my D600 system running RH9 and now FC2, it's
been better and better.
On RH9, 2.4 kernel, I had to switch to virtual terminal before I get
back my display. No 3D/dri support
Rh9 2.6 kernel, no need to switch to VT. Still no 3D.
Fc2 2.6 kernel. No need for VT and There's DRI/3d (Tux racer works
Great/fast)
But I keep complaining because I can't run America's Army and Unreal
Tournament etc.
>
> I have no experience with S3 suspend (my laptop doesn't seem to support
> it) but it does suspend with swsusp2 if I switch VT.
S3 is a different beast. I believe it's the code implementation. I heard
that FreeBSD users seems to be able to get it working.
Linux Users are getting there too. (Debian) and what I've heard but not
understood is the Need for POSTing the VGA card.
S4 works for Me. S3 Nope.
> > Regards,
> > Andrew Barr
> >
> >
> >
> > -------------------------------------------------------
> > This SF.Net email is sponsored by OSTG. Have you noticed the changes on
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> > _______________________________________________
> > Acpi-devel mailing list
> > Acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
> > https://lists.sourceforge.net/lists/listinfo/acpi-devel
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> > +++++++++++++++++++++++++++++++++++++++++++
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>
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--
Ow Mun Heng
Fedora GNU/Linux Core 2 on D600 1.4Ghz CPU kernel
2.6.7-2.jul1-interactive
Neuromancer 13:05:47 up 4:24, 6 users, load average: 2.36, 1.96, 2.44
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* Re: Radeon PM Support
[not found] ` <88056F38E9E48644A0F562A38C64FB60028F9AC3-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
@ 2004-08-07 6:34 ` Alexander Bruder
2004-08-11 19:08 ` Pavel Machek
1 sibling, 0 replies; 54+ messages in thread
From: Alexander Bruder @ 2004-08-07 6:34 UTC (permalink / raw)
To: Pallipadi, Venkatesh
Cc: ole.rohne-vJEk5272eHo, Nathan Bryant,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
> I am still wondering why it doesn't work for Alexander.
> Alexander: Is your card sitting on PCI or AGP?
AGP
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* Re: Radeon PM Support
[not found] ` <yzo7jscnyyu.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-06 19:09 ` Stefan Dösinger
@ 2004-08-08 14:53 ` Stefan Schweizer
1 sibling, 0 replies; 54+ messages in thread
From: Stefan Schweizer @ 2004-08-08 14:53 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo@public.gmane.org
Cc: Nathan Bryant, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
[...]
> Nathan> Maybe we need proper AGP save/restore before we can POST?
[...]
> This could be a possible explanation for the problems that the two
> Stefans are seeing: POSTing with XFree86 works because XFree86 does
> the AGP restoration.
>
> Ole
Can i help here somewhere? Can I do something to solve the 2 issues I see?
The need to press a key makes the resume time very long.
And mobile computing without games because of intel-agp is not really a joy ..
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* RE: Radeon PM Support
[not found] ` <88056F38E9E48644A0F562A38C64FB600289AE7C-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2004-08-06 6:29 ` ole.rohne-vJEk5272eHo
2004-08-06 15:03 ` Alexander Bruder
@ 2004-08-11 17:32 ` Matthew Garrett
2004-08-19 11:17 ` Pavel Machek
2 siblings, 1 reply; 54+ messages in thread
From: Matthew Garrett @ 2004-08-11 17:32 UTC (permalink / raw)
To: Pallipadi, Venkatesh
Cc: anib-La3J9u0raUk, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
On Thu, 2004-08-05 at 10:52 -0700, Pallipadi, Venkatesh wrote:
> Does this addon patch (over the Ole's original patch) help?
With a Thinkpad X40 (Intel 855GM graphics chipset), this stops resume
from working. acpi_sleep=s3_bios works.
--
Matthew Garrett | mjg59-1xO5oi07KQx4cg9Nei1l7Q@public.gmane.org
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^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: Radeon PM Support
@ 2004-08-11 17:47 Pallipadi, Venkatesh
[not found] ` <88056F38E9E48644A0F562A38C64FB600296CFD2-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Pallipadi, Venkatesh @ 2004-08-11 17:47 UTC (permalink / raw)
To: Matthew Garrett
Cc: anib-La3J9u0raUk, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
>-----Original Message-----
>From: Matthew Garrett [mailto:mjg59-1xO5oi07KQx4cg9Nei1l7Q@public.gmane.org]
>Sent: Wednesday, August 11, 2004 10:32 AM
>To: Pallipadi, Venkatesh
>Cc: anib-La3J9u0raUk@public.gmane.org; acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org;
>stefandoesinger-RbZlAiThDcE@public.gmane.org
>Subject: RE: [ACPI] Radeon PM Support
>
>On Thu, 2004-08-05 at 10:52 -0700, Pallipadi, Venkatesh wrote:
>> Does this addon patch (over the Ole's original patch) help?
>
>With a Thinkpad X40 (Intel 855GM graphics chipset), this stops resume
>from working. acpi_sleep=s3_bios works.
>
How was it working before you applied this patch? By default? Or with
acpi_sleep=s3_bios?
With this patch does it stop working completely or does it work with
acpi_sleep=s3_bios option?
Thanks,
Venki
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^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: Radeon PM Support
[not found] ` <88056F38E9E48644A0F562A38C64FB600296CFD2-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
@ 2004-08-11 17:51 ` Matthew Garrett
2004-08-12 5:34 ` ole.rohne-vJEk5272eHo
0 siblings, 1 reply; 54+ messages in thread
From: Matthew Garrett @ 2004-08-11 17:51 UTC (permalink / raw)
To: Pallipadi, Venkatesh
Cc: anib-La3J9u0raUk, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
On Wed, 2004-08-11 at 10:47 -0700, Pallipadi, Venkatesh wrote:
> How was it working before you applied this patch? By default? Or with
> acpi_sleep=s3_bios?
Ah, sorry. Before it worked with acpi_sleep=s3_bios, but not by
default.
> With this patch does it stop working completely or does it work with
> acpi_sleep=s3_bios option?
Without acpi_sleep=s3_bios, the screen remains black. With
acpi_sleep=s3_bios, the backlight comes back on but I get no video
output. The machine doesn't appear to be alive at this point.
--
Matthew Garrett | mjg59-1xO5oi07KQx4cg9Nei1l7Q@public.gmane.org
-------------------------------------------------------
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <88056F38E9E48644A0F562A38C64FB60028F9AC3-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2004-08-07 6:34 ` Alexander Bruder
@ 2004-08-11 19:08 ` Pavel Machek
[not found] ` <20040811190824.GF1120-u08AdweFZfgxtPtxi4kahqVXKuFTiq87@public.gmane.org>
1 sibling, 1 reply; 54+ messages in thread
From: Pavel Machek @ 2004-08-11 19:08 UTC (permalink / raw)
To: Pallipadi, Venkatesh
Cc: ole.rohne-vJEk5272eHo, Nathan Bryant,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, anib-La3J9u0raUk
Hi!
> > I"ve been hesitant to propose a generic VGAPOST, but it could be good
> > to have a way of resuming without using a driver. Would it be cleaner
> > to put the call in pci_default_resume?
>
> Yes. If this patch works for tohers, then we can move it into
> pci_default_resume during the cleanup.
I'd rather not do that. Some cards are already posted after
S3, some even preserve state over S3. It is okay to do VGAPOST
for radeon and any card that needs it, but I'd rather not do it generically.
--
64 bytes from 195.113.31.123: icmp_seq=28 ttl=51 time=448769.1 ms
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <yzosmb0hjzu.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
2004-08-06 13:39 ` Nathan Bryant
2004-08-06 13:58 ` Andi Kleen
@ 2004-08-11 19:39 ` Pavel Machek
2 siblings, 0 replies; 54+ messages in thread
From: Pavel Machek @ 2004-08-11 19:39 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo
Cc: Len Brown, Acpi Devel, Erik Tews, Nathan Bryant, Andrew Barr
Hi!
> Len> I would like a solution that applies to x86_64 in addition to
> Len> i386.
>
> What would it take?
Len, you can't expect ole to write x86-64 support without testing.
Patch should be designed so that it does no damage on non-i386, but
you should not expect more.
It would be nice if i386 version could be merged. I'll probably do
x86-64 in future; stable i386 version
would certainly help me.
> I know absolutely nothing about that architecture. From
> arch/x86_64/kernel/acpi/wakeup.S it seems to support some form of real
> mode, so could it do the return to real mode just like i386?
Yes.
> "lkml" - is that the linux kernel mailing list?
Yes.
Pavel
--
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^ permalink raw reply [flat|nested] 54+ messages in thread
* RE: Radeon PM Support
@ 2004-08-11 20:36 Pallipadi, Venkatesh
0 siblings, 0 replies; 54+ messages in thread
From: Pallipadi, Venkatesh @ 2004-08-11 20:36 UTC (permalink / raw)
To: Pavel Machek
Cc: ole.rohne-vJEk5272eHo, Nathan Bryant,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, anib-La3J9u0raUk
>-----Original Message-----
>From: Pavel Machek [mailto:pavel-+ZI9xUNit7I@public.gmane.org]
>Sent: Wednesday, August 11, 2004 12:08 PM
>To: Pallipadi, Venkatesh
>Cc: ole.rohne-vJEk5272eHo@public.gmane.org; Nathan Bryant;
>acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org; anib-La3J9u0raUk@public.gmane.org
>Subject: Re: [ACPI] Radeon PM Support
>
>Hi!
>
>> > I"ve been hesitant to propose a generic VGAPOST, but it
>could be good
>> > to have a way of resuming without using a driver. Would it
>be cleaner
>> > to put the call in pci_default_resume?
>>
>> Yes. If this patch works for tohers, then we can move it into
>> pci_default_resume during the cleanup.
>
>
>I'd rather not do that. Some cards are already posted after
>S3, some even preserve state over S3.
> It is okay to do VGAPOST
>for radeon and any card that needs it, but I'd rather not do
>it generically.
If this is the right place to do post for most of the devices,
then probably we can do away with initial soon-after-wakeup-post.
Right?
But, for the devices that preserve state, yes we need to avoid
doing this. I can see one more device-blacklist/whitelist coming
here :).
Thanks,
Venki
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
2004-08-11 17:51 ` Matthew Garrett
@ 2004-08-12 5:34 ` ole.rohne-vJEk5272eHo
0 siblings, 0 replies; 54+ messages in thread
From: ole.rohne-vJEk5272eHo @ 2004-08-12 5:34 UTC (permalink / raw)
To: Matthew Garrett
Cc: Pallipadi, Venkatesh, anib-La3J9u0raUk,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
Matthew> Without acpi_sleep=s3_bios, the screen remains black. With
Matthew> acpi_sleep=s3_bios, the backlight comes back on but I get no
Matthew> video output. The machine doesn't appear to be alive at this
Matthew> point.
Is your adapter perhaps on AGP? Did you see the patch to include the
bus number with the slot:function argument?
Ole
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <yzo4qngh7ji.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
2004-08-06 12:32 ` Stefan Schweizer
@ 2004-08-12 14:30 ` Stefan Schweizer
1 sibling, 0 replies; 54+ messages in thread
From: Stefan Schweizer @ 2004-08-12 14:30 UTC (permalink / raw)
To: ole.rohne-vJEk5272eHo@public.gmane.org,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Hello ole,
Your patch has another problem: it even "works" on s4 (suspend-to-disk)
That means 2 times a blacklight and a return and the need for a keypress.
But it is absolutely not necessary on suspend-to-disk we only need it
on suspend to ram.
Do you still work on the patch? Is there a newer version to test?
Stefan
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <20040811190824.GF1120-u08AdweFZfgxtPtxi4kahqVXKuFTiq87@public.gmane.org>
@ 2004-08-12 16:05 ` Stefan Seyfried
0 siblings, 0 replies; 54+ messages in thread
From: Stefan Seyfried @ 2004-08-12 16:05 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
On Wed, Aug 11, 2004 at 09:08:24PM +0200, Pavel Machek wrote:
> Hi!
>
> > Yes. If this patch works for tohers, then we can move it into
> > pci_default_resume during the cleanup.
>
>
> I'd rather not do that. Some cards are already posted after
> S3, some even preserve state over S3. It is okay to do VGAPOST
> for radeon and any card that needs it, but I'd rather not do it generically.
what about "acpi_sleep=vgapost"?
--
Stefan Seyfried
-------------------------------------------------------
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
2004-08-11 17:32 ` Matthew Garrett
@ 2004-08-19 11:17 ` Pavel Machek
0 siblings, 0 replies; 54+ messages in thread
From: Pavel Machek @ 2004-08-19 11:17 UTC (permalink / raw)
To: Matthew Garrett
Cc: Pallipadi, Venkatesh, anib-La3J9u0raUk,
acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
stefandoesinger-RbZlAiThDcE
Hi!
> > Does this addon patch (over the Ole's original patch) help?
>
> With a Thinkpad X40 (Intel 855GM graphics chipset), this stops resume
> from working. acpi_sleep=s3_bios works.
Same behaviour on amd64 desktop :-(.
Pavel
--
People were complaining that M$ turns users into beta-testers...
...jr ghea gurz vagb qrirybcref, naq gurl frrz gb yvxr vg gung jnl!
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
2004-08-19 14:03 Pallipadi, Venkatesh
@ 2004-08-19 15:37 ` Aman Gupta
2004-08-19 15:54 ` Stefan Dösinger
1 sibling, 0 replies; 54+ messages in thread
From: Aman Gupta @ 2004-08-19 15:37 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Pallipadi, Venkatesh <venkatesh.pallipadi@...> writes:
>
> I guess we need to do something like this "acpi_sleep=vgapost",
> rather than doing a generic vgapost for all display devices.
> As the generic solution seems to have broken few systems
> which were working before.
>
> I have two systems with almost identical video setup, with
> Radeon 9000M AGP adapter. vgapost works on one system and
> fails on another. The failing system never returns
> from real mode vgapost call. I also found that
> the VBIOS is not same on these two systems. Probably
> different versions of the firmware. I am digging further
> to find out why it works on one Radeon 9000M and not
> on another one.
>
> -Venki
Does vgapost work if you do it on the commandline using the
http://www.doesi.gmxhome.de/linux/tm800s3/resources/boot-radeon.c utility? Are
there any differences in the lspci -vv output of the two cards? Are they both on
1:0.0?
Can you post a patch that implements acpi_sleep=vgapost so it can be tested on
different systems?
Aman Gupta
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <200408052153.25467.stefandoesinger-RbZlAiThDcE@public.gmane.org>
@ 2004-08-19 17:43 ` Luca
[not found] ` <20040819174319.GB6913-sTXFmx6KbOnUXq0IF5SVAZ4oGUkBHcCu@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Luca @ 2004-08-19 17:43 UTC (permalink / raw)
To: Stefan Dösinger
Cc: anib-La3J9u0raUk, acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Il Thu, Aug 05, 2004 at 09:53:25PM +0200, Stefan Dösinger ha scritto:
> *the boot-radeon.c program can ROM-post the radeon card(compile with gcc
> boot-radeon.c -o boot-radeon -llrmi) You need the lrmi libs+headers. Call it
> after resuming from S3.
Is this radeon specific? AFAICS it should POST any card, right?
Oh, one small bug:
> void err(char *function, int exitval) {
> fprintf(stderr, "%s():\n");
fprintf(stderr, "%s():\n", function);
Luca
--
Home: http://kronoz.cjb.net
Runtime error 6D at f000:a12f : user incompetente
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <20040819174319.GB6913-sTXFmx6KbOnUXq0IF5SVAZ4oGUkBHcCu@public.gmane.org>
@ 2004-08-19 18:38 ` Stefan Dösinger
[not found] ` <200408192038.26959.stefandoesinger-RbZlAiThDcE@public.gmane.org>
0 siblings, 1 reply; 54+ messages in thread
From: Stefan Dösinger @ 2004-08-19 18:38 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
kronos-0Y2hHv2PMqFeoWH0uzbU5w
Cc: anib-La3J9u0raUk
> > *the boot-radeon.c program can ROM-post the radeon card(compile with gcc
> > boot-radeon.c -o boot-radeon -llrmi) You need the lrmi libs+headers. Call
> > it after resuming from S3.
>
> Is this radeon specific? AFAICS it should POST any card, right?
Ole Rohne says it's an old IBM PC feature:
"It is an old IBM PC like feature...
If the adapter has BIOS at $0xc000, it is supposed to contain a POST
entry point at $0xc000,$3 and int10/e6 is supposed to point to it."
Just give it a try. Note that the boot-radeon.c has the PCI information 1:0:0
hardcoded, so you'll have to edit it if your video card is somewhere else.
Stefan
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
[not found] ` <200408192038.26959.stefandoesinger-RbZlAiThDcE@public.gmane.org>
@ 2004-08-19 20:03 ` Luca
0 siblings, 0 replies; 54+ messages in thread
From: Luca @ 2004-08-19 20:03 UTC (permalink / raw)
To: Stefan Dösinger
Cc: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
kronos-0Y2hHv2PMqFeoWH0uzbU5w
Il Thu, Aug 19, 2004 at 08:38:26PM +0200, Stefan Dösinger ha scritto:
> *This message was transferred with a trial version of CommuniGate(tm) Pro*
> > > *the boot-radeon.c program can ROM-post the radeon card(compile with gcc
> > > boot-radeon.c -o boot-radeon -llrmi) You need the lrmi libs+headers. Call
> > > it after resuming from S3.
> >
> > Is this radeon specific? AFAICS it should POST any card, right?
> Ole Rohne says it's an old IBM PC feature:
>
> "It is an old IBM PC like feature...
>
> If the adapter has BIOS at $0xc000, it is supposed to contain a POST
> entry point at $0xc000,$3 and int10/e6 is supposed to point to it."
>
> Just give it a try. Note that the boot-radeon.c has the PCI information 1:0:0
> hardcoded, so you'll have to edit it if your video card is somewhere else.
I'll give it a try when my notebook comes back from RMA...
The BIOS on my desktop runs the VGA BIOS on S3 resume by itself.
Luca
--
Home: http://kronoz.cjb.net
Carpe diem, quam minimum credula postero. (Q. Horatius Flaccus)
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: Radeon PM Support
2004-08-19 15:54 ` Stefan Dösinger
@ 2004-08-19 20:39 ` Aman Gupta
0 siblings, 0 replies; 54+ messages in thread
From: Aman Gupta @ 2004-08-19 20:39 UTC (permalink / raw)
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Stefan Dösinger <stefandoesinger@...> writes:
> Interesting: vgapost failes on my Acer Travelmate 803(radeon mobility 9000)
> and Ole and I couldn't find any reason so far. How did you check what vbios
> your radeon card has?
>
> Does user-mode vgapost work for you? Strangely it does on my system.
>
> Stefan
Can you post your lspci -vv and we can compare it with the two from Venki and
maybe figure out whats going on.
Aman Gupta
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^ permalink raw reply [flat|nested] 54+ messages in thread
end of thread, other threads:[~2004-08-19 20:39 UTC | newest]
Thread overview: 54+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2004-08-11 17:47 Radeon PM Support Pallipadi, Venkatesh
[not found] ` <88056F38E9E48644A0F562A38C64FB600296CFD2-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2004-08-11 17:51 ` Matthew Garrett
2004-08-12 5:34 ` ole.rohne-vJEk5272eHo
-- strict thread matches above, loose matches on Subject: below --
2004-08-19 14:03 Pallipadi, Venkatesh
2004-08-19 15:37 ` Aman Gupta
2004-08-19 15:54 ` Stefan Dösinger
2004-08-19 20:39 ` Aman Gupta
2004-08-11 20:36 Pallipadi, Venkatesh
2004-08-06 16:35 Pallipadi, Venkatesh
[not found] ` <88056F38E9E48644A0F562A38C64FB60028F9AC3-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2004-08-07 6:34 ` Alexander Bruder
2004-08-11 19:08 ` Pavel Machek
[not found] ` <20040811190824.GF1120-u08AdweFZfgxtPtxi4kahqVXKuFTiq87@public.gmane.org>
2004-08-12 16:05 ` Stefan Seyfried
2004-08-05 17:52 Pallipadi, Venkatesh
[not found] ` <88056F38E9E48644A0F562A38C64FB600289AE7C-exJ48ZlmiLpQxe9IK+vIArfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2004-08-06 6:29 ` ole.rohne-vJEk5272eHo
[not found] ` <e796392204080601016e29a349@mail.gmail.com>
[not found] ` <yzo4qngh7ji.fsf@pb-d-128-141-40-189.cern.ch>
[not found] ` <yzo4qngh7ji.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
2004-08-06 12:32 ` Stefan Schweizer
[not found] ` <e796392204080605327588e5ac-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2004-08-06 13:38 ` Nathan Bryant
2004-08-12 14:30 ` Stefan Schweizer
2004-08-06 15:03 ` Alexander Bruder
2004-08-11 17:32 ` Matthew Garrett
2004-08-19 11:17 ` Pavel Machek
2004-07-29 22:14 Andrew Barr
[not found] ` <1091139240.26511.9.camel-0uShlLfvWR/1N/xxgP7OLA@public.gmane.org>
2004-07-30 14:10 ` Micha Feigin
[not found] ` <20040730141028.GE21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
2004-07-30 13:31 ` Andrew Barr
2004-07-30 14:27 ` wwp
[not found] ` <20040730162756.4f300a5c-bi+AKbBUZKZeoWH0uzbU5w@public.gmane.org>
2004-07-30 19:00 ` Micha Feigin
[not found] ` <20040730190047.GH21359-4cxDFgrrBECgSpxsJD1C4w@public.gmane.org>
2004-08-03 19:10 ` Andrew Barr
2004-08-03 23:23 ` Erik Tews
2004-08-04 1:18 ` Nathan Bryant
[not found] ` <41103952.2030707-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
2004-08-04 1:33 ` Erik Tews
[not found] ` <1091583216.2974.2.camel-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-04 3:40 ` Len Brown
2004-08-04 6:43 ` ole.rohne-vJEk5272eHo
[not found] ` <yzohdrjqu6p.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-04 7:17 ` Ow Mun Heng
2004-08-04 7:17 ` wwp
2004-08-04 14:52 ` Len Brown
2004-08-04 17:44 ` count0-tC47gz4GrgtWk0Htik3J/w
[not found] ` <52654.199.172.169.15.1091641493.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
2004-08-04 17:48 ` Nathan Bryant
[not found] ` <4111217B.8000900-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
2004-08-04 18:23 ` count0-tC47gz4GrgtWk0Htik3J/w
[not found] ` <62466.199.172.169.15.1091643791.squirrel-2RFepEojUI20LjuDPgauC1aTQe2KTcn/@public.gmane.org>
2004-08-04 18:35 ` Eric Valette
2004-08-04 19:00 ` Stefan Dösinger
[not found] ` <200408042100.24705.stefandoesinger-RbZlAiThDcE@public.gmane.org>
2004-08-05 7:33 ` ole.rohne-vJEk5272eHo
[not found] ` <yzo7jse5999.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-05 12:27 ` Tomasz Ciolek
2004-08-05 12:53 ` Stefan Dösinger
[not found] ` <200408051453.55710.stefandoesinger-RbZlAiThDcE@public.gmane.org>
2004-08-05 17:14 ` Alexander Bruder
[not found] ` <200408051914.39445.anib-La3J9u0raUk@public.gmane.org>
2004-08-05 19:53 ` Stefan Dösinger
[not found] ` <200408052153.25467.stefandoesinger-RbZlAiThDcE@public.gmane.org>
2004-08-19 17:43 ` Luca
[not found] ` <20040819174319.GB6913-sTXFmx6KbOnUXq0IF5SVAZ4oGUkBHcCu@public.gmane.org>
2004-08-19 18:38 ` Stefan Dösinger
[not found] ` <200408192038.26959.stefandoesinger-RbZlAiThDcE@public.gmane.org>
2004-08-19 20:03 ` Luca
2004-08-06 20:03 ` Ow Mun Heng
2004-08-06 6:13 ` ole.rohne-vJEk5272eHo
[not found] ` <yzosmb0hjzu.fsf-1zyhLZfD728Z/JH0GhYu5ApX6sy8U9uuH79+75y5D5U@public.gmane.org>
2004-08-06 13:39 ` Nathan Bryant
[not found] ` <41138A16.5000908-p32f3XyCuykqcZcGjlUOXw@public.gmane.org>
2004-08-06 14:05 ` ole.rohne-vJEk5272eHo
[not found] ` <yzo7jscnyyu.fsf-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2004-08-06 19:09 ` Stefan Dösinger
2004-08-08 14:53 ` Stefan Schweizer
2004-08-06 13:58 ` Andi Kleen
2004-08-11 19:39 ` Pavel Machek
2004-08-06 20:10 ` Ow Mun Heng
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