RE: [PATCH] amd76x_pm: C3 powersaving for AMD K7

[Erik Slagter <erik@slagter.name>]

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On Fri, 2006-02-03 at 03:45 -0500, Brown, Len wrote:
>  >... I disagree with Len in two points:
> >- I cannot see a problem witch cache snooping.
> >  The AMD-768 docs clearly
> >  states that trying to snoop the cache while in C3 is a resume event.
> 
> Certainly the BIOS writer also had access to that document, plus
> documents we do not see, yet they decided NOT to enable C2/C3.

You are probably right, but I remain suspicious that the BIOS writers
simply didn't want to go through the trouble of implementing and testing
the whole thing, presumable because:

 - who wants to have power saving on a dual processor board anyway
(well, I do, but that's just me)
 - every line of code takes time to write and test and debug, it
wouldn't quite be the first occurrence of buggy or marginal "firmware",
have a look at some harddisks :-(

If I remember correctly there was some sort of windows driver supplied
with the board to enable power saving. This would suggest that in
principle there is no reason it cannot work.

> Who defines the "right way"?  Is it guaranteed to work on all
> models and all configurations?  Exactly what is the reward
> for the cost we'd be paying and the risk we'd be taking?

The advantage is that we're talking about only 1.5 chipset here with
very few revisions. Okay, this still leaves the board manufacturer that
can do what they want.

> If somebody from AMD steps forth and says that hey, their hardware
> is broken if used in the standard way, but that this "logic around"
> is a valid model-specific workaround -- then we have something
> that MAYBE we can work with.

Yeah, that would be nice. But I guess _someone_ will have to poke them a
bit first...


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