From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Eric W. Biederman" Subject: [PATCH 20/25] irq: Generalize the check for HARDIRQ_BITS. Date: Tue, 20 Jun 2006 16:28:33 -0600 Message-ID: <11508425253581-git-send-email-ebiederm@xmission.com> References: <11508425183073-git-send-email-ebiederm@xmission.com> <11508425191381-git-send-email-ebiederm@xmission.com> <11508425192220-git-send-email-ebiederm@xmission.com> <11508425191063-git-send-email-ebiederm@xmission.com> <1150842520235-git-send-email-ebiederm@xmission.com> <11508425201406-git-send-email-ebiederm@xmission.com> <1150842520775-git-send-email-ebiederm@xmission.com> <11508425213394-git-send-email-ebiederm@xmission.com> <115084252131-git-send-email-ebiederm@xmission.com> <11508425213795-git-send-email-ebiederm@xmission.com> <11508425222427-git-send-email-ebiederm@xmission.com> <11508425221394-git-send-email-ebiederm@xmission.com> <11508425223015-git-send-email-ebiederm@xmission.com> <1150842523493-git-send-email-ebiederm@xmission.com> <11508425231168-git-send-email-ebiederm@xmission.com> <1150842524863-git-send-email-ebiederm@x mission.com> <1150842524755-git-send-email-ebiederm@xmission.com> <115084252460-git-send-! email-ebiederm@xmission.com> <11508425251099-git-send-email-ebiederm@xmission.com> Reply-To: "Eric W. Biederman" Return-path: In-Reply-To: <11508425251099-git-send-email-ebiederm@xmission.com> Sender: linux-kernel-owner@vger.kernel.org To: Andrew Morton Cc: linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pci@atrey.karlin.mff.cuni.cz, discuss@x86-64.org, Ingo Molnar , Thomas Gleixner , Andi Kleen , Natalie Protasevich , Len Brown , Kimball Murray , Brice Goglin , Greg Lindahl , Dave Olson , Jeff Garzik , Greg KH , Grant Grundler , "bibo,mao" , Rajesh Shah , Mark Maule , Jesper Juhl , Shaohua Li , Matthew Wilcox , "Michael S. Tsirkin" , Ashok Raj , Randy Dunlap Roland Dreier List-Id: linux-acpi@vger.kernel.org This patch adds support for systems that cannot receive every interrupt on a single cpu simultaneously, in the check to see if we have enough HARDIRQ_BITS. MAX_HARDIRQS_PER_CPU becomes the count of the maximum number of hardare generated interrupts per cpu. On architectures that support per cpu interrupt delivery this can be a significant space savings and scalability bonus. This patch adds support for systems that cannot receive every interrupt on Signed-off-by: Eric W. Biederman --- include/asm-x86_64/hardirq.h | 3 +++ include/linux/hardirq.h | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/include/asm-x86_64/hardirq.h b/include/asm-x86_64/hardirq.h index 64a65ce..95d5e09 100644 --- a/include/asm-x86_64/hardirq.h +++ b/include/asm-x86_64/hardirq.h @@ -6,6 +6,9 @@ #include #include #include +/* We can have at most NR_VECTORS irqs routed to a cpu at a time */ +#define MAX_HARDIRQS_PER_CPU NR_VECTORS + #define __ARCH_IRQ_STAT 1 #define local_softirq_pending() read_pda(__softirq_pending) diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h index ccabda7..f60b8c3 100644 --- a/include/linux/hardirq.h +++ b/include/linux/hardirq.h @@ -27,11 +27,16 @@ #define SOFTIRQ_BITS 8 #ifndef HARDIRQ_BITS #define HARDIRQ_BITS 12 + +#ifndef MAX_HARDIRQS_PER_CPU +#define MAX_HARDIRQS_PER_CPU NR_IRQS +#endif + /* * The hardirq mask has to be large enough to have space for potentially * all IRQ sources in the system nesting on a single CPU. */ -#if (1 << HARDIRQ_BITS) < NR_IRQS +#if (1 << HARDIRQ_BITS) < MAX_HARDIRQS_PER_CPU # error HARDIRQ_BITS is too low! #endif #endif -- 1.4.0.gc07e