From mboxrd@z Thu Jan  1 00:00:00 1970
From: Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH -v4 1/2] lib, Make gen_pool memory allocator lockless
Date: Thu, 18 Nov 2010 09:34:35 +0100
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To: Huang Ying <ying.huang@intel.com>
Cc: huang ying <huang.ying.caritas@gmail.com>, Andrew Morton <akpm@linux-foundation.org>, Len Brown <lenb@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Andi Kleen <andi@firstfloor.org>, "linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>, Linus Torvalds <torvalds@linux-foundation.org>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>, Mauro Carvalho Chehab <mchehab@redhat.com>, Paul Mundt <lethal@linux-sh.org>

On Thu, 2010-11-18 at 09:14 +0800, Huang Ying wrote:
> On Wed, 2010-11-17 at 19:53 +0800, Peter Zijlstra wrote:
> > On Wed, 2010-11-17 at 19:47 +0800, huang ying wrote:
> > > On Wed, Nov 17, 2010 at 6:40 PM, Peter Zijlstra <peterz@infradead.org> wrote:
> > > > On Wed, 2010-11-17 at 10:18 +0800, Huang Ying wrote:
> > > >>
> > > >> cmpxchg has been used in that way by ftrace and perf for a long time. So
> > > >> I agree to make it a requirement on future architecture ports.
> > > >
> > > > Neither mandate an architecture do this though, only that when an
> > > > architecture wants to support either feature and has NMIs (not all archs
> > > > have NMI equivalents) it has to be safe.
> > > 
> > > So we can make sure cmpxchg can be used in lock-less code on
> > > architectures with perf, irq_work or ftrace enabled?
> > 
> > It had better, otherwise stuff is broken.
> 
> Take a look at superh architecture cmpxchg implementation. It seems that
> cmpxchg is implemented with special instruction if CONFIG_GUSA_RB=y or
> CONFIG_CPU_SH4A=y, otherwise it is implemented with local_irq_save. Is
> it possible that superh has not PMU support if CONFIG_GUSA_RB=n and
> CONFIG_CPU_SH4A=n, so that perf work properly but no NMI safe cmpxchg in
> that situation?

Dunno, you forgot to CC the author of that code.. I've really no clue
about SH.