[PATCH 0/2] ACPI / LPSS: fractional divider clocks

[PATCH 0/2] ACPI / LPSS: fractional divider clocks

[Heikki Krogerus]

Hi,

This serie is about getting support for the m over n fractional
divisors that are available for SPI and UART in Intel LPSS. We will
need support for it with the UART.

Fractional dividers appear to be quite common so I'm suggesting a new
basic clk type for them in the first patch.


Heikki Krogerus (2):
  clk: new basic clk type for fractional divider
  ACPI / LPSS: Support for fractional divider clock

 drivers/acpi/acpi_lpss.c             |  37 ++++++++--
 drivers/clk/Makefile                 |   1 +
 drivers/clk/clk-fractional-divider.c | 132 +++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h         |  31 ++++++++
 4 files changed, 194 insertions(+), 7 deletions(-)
 create mode 100644 drivers/clk/clk-fractional-divider.c

-- 
2.0.0.rc0

[PATCH 1/2] clk: new basic clk type for fractional divider

[Heikki Krogerus]

Fractional divider clocks are fairly common. This adds basic
type for them.

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
---
 drivers/clk/Makefile                 |   1 +
 drivers/clk/clk-fractional-divider.c | 132 +++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h         |  31 ++++++++
 3 files changed, 164 insertions(+)
 create mode 100644 drivers/clk/clk-fractional-divider.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f8a287..0745059 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-fractional-divider.o
 
 # hardware specific clock types
 # please keep this section sorted lexicographically by file/directory path name
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
new file mode 100644
index 0000000..a4dd873
--- /dev/null
+++ b/drivers/clk/clk-fractional-divider.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable fractional divider clock implementation.
+ * Output rate = (m / n) * parent_rate.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/gcd.h>
+
+#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
+
+static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
+					unsigned long parent_rate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long flags = 0;
+	unsigned n, m;
+	u32 val;
+
+	if (fd->lock)
+		spin_lock_irqsave(fd->lock, flags);
+
+	val = clk_readl(fd->reg);
+
+	if (fd->lock)
+		spin_unlock_irqrestore(fd->lock, flags);
+
+	m = (val & fd->mmask) >> fd->mshift;
+	n = (val & fd->nmask) >> fd->nshift;
+
+	return parent_rate / n * m;
+}
+
+static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *prate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned maxdiv = (fd->nmask >> fd->nshift) + 1;
+	unsigned div;
+
+	if (!rate || rate > *prate)
+		return *prate;
+
+	div = gcd(*prate, rate);
+
+	while ((*prate / div) > maxdiv) {
+		div <<= 1;
+		rate <<= 1;
+	}
+
+	return rate;
+}
+
+static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
+			   unsigned long parent_rate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long flags = 0;
+	unsigned long div;
+	unsigned n, m;
+	u32 val;
+
+	div = gcd(parent_rate, rate);
+	m = rate / div;
+	n = parent_rate / div;
+
+	if (fd->lock)
+		spin_lock_irqsave(fd->lock, flags);
+
+	val = clk_readl(fd->reg);
+	val &= ~(fd->mmask | fd->nmask);
+	val |= (m << fd->mshift) | (n << fd->nshift);
+	clk_writel(val, fd->reg);
+
+	if (fd->lock)
+		spin_unlock_irqrestore(fd->lock, flags);
+
+	return 0;
+}
+
+const struct clk_ops clk_fractional_divider_ops = {
+	.recalc_rate = clk_fd_recalc_rate,
+	.round_rate = clk_fd_round_rate,
+	.set_rate = clk_fd_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
+
+struct clk *clk_register_fractional_divider(struct device *dev,
+		const char *name, const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
+		u8 clk_divider_flags, spinlock_t *lock)
+{
+	struct clk_fractional_divider *fd;
+	struct clk_init_data init;
+	struct clk *clk;
+
+	fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+	if (!fd) {
+		pr_err("%s: could not allocate fractional divider clk\n",
+		       __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &clk_fractional_divider_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	fd->reg = reg;
+	fd->mshift = mshift;
+	fd->mmask = (BIT(mwidth) - 1) << mshift;
+	fd->nshift = nshift;
+	fd->nmask = (BIT(nwidth) - 1) << nshift;
+	fd->flags = clk_divider_flags;
+	fd->lock = lock;
+	fd->hw.init = &init;
+
+	clk = clk_register(dev, &fd->hw);
+	if (IS_ERR(clk))
+		kfree(fd);
+
+	return clk;
+}
+EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5119174..fb4eca6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -413,6 +413,37 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
 
+/**
+ * struct clk_fractional_divider - adjustable fractional divider clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register containing the divider
+ * @mshift:	shift to the numerator bit field
+ * @mwidth:	width of the numerator bit field
+ * @nshift:	shift to the denominator bit field
+ * @nwidth:	width of the denominator bit field
+ * @lock:	register lock
+ *
+ * Clock with adjustable fractional divider affecting its output frequency.
+ */
+
+struct clk_fractional_divider {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		mshift;
+	u32		mmask;
+	u8		nshift;
+	u32		nmask;
+	u8		flags;
+	spinlock_t	*lock;
+};
+
+extern const struct clk_ops clk_fractional_divider_ops;
+struct clk *clk_register_fractional_divider(struct device *dev,
+		const char *name, const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
+		u8 clk_divider_flags, spinlock_t *lock);
+
 /***
  * struct clk_composite - aggregate clock of mux, divider and gate clocks
  *
-- 
2.0.0.rc0

[PATCH 2/2] ACPI / LPSS: Support for fractional divider clock

[Heikki Krogerus]

The dividers are available for UART and SPI on both
Lynxpoint and Baytrail. With SPI, handling the dividers is
optional, but in case of UART they should be adjusted
according to the requested baud rate.

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
---
 drivers/acpi/acpi_lpss.c | 37 ++++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 69e29f4..508ac9f 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -58,6 +58,7 @@ struct lpss_device_desc {
 	unsigned int prv_offset;
 	size_t prv_size_override;
 	bool clk_gate;
+	bool clk_divider;
 	struct lpss_shared_clock *shared_clock;
 	void (*setup)(struct lpss_private_data *pdata);
 };
@@ -119,16 +120,11 @@ static struct lpss_device_desc byt_pwm_dev_desc = {
 	.shared_clock = &pwm_clock,
 };
 
-static struct lpss_shared_clock uart_clock = {
-	.name = "uart_clk",
-	.rate = 44236800,
-};
-
 static struct lpss_device_desc byt_uart_dev_desc = {
 	.clk_required = true,
 	.prv_offset = 0x800,
 	.clk_gate = true,
-	.shared_clock = &uart_clock,
+	.clk_divider = true,
 	.setup = lpss_uart_setup,
 };
 
@@ -246,8 +242,35 @@ static int register_device_clock(struct acpi_device *adev,
 		parent = shared_clock->name;
 	}
 
+	if (dev_desc->clk_divider) {
+		char *name = kzalloc(strlen(dev_name(&adev->dev)) + 8,
+				     GFP_KERNEL);
+		if (!name)
+			return -ENOMEM;
+		strcpy(name, "div_clk-");
+		strcat(name, dev_name(&adev->dev));
+
+		clk = clk_register_fractional_divider(NULL, name, parent, 0,
+					pdata->mmio_base + dev_desc->prv_offset,
+					1, 15, 16, 15, 0, NULL);
+		parent = name;
+
+		name = kzalloc(strlen(dev_name(&adev->dev)) + 11, GFP_KERNEL);
+		if (!name)
+			return -ENOMEM;
+		strcpy(name, "clk_update-");
+		strcat(name, dev_name(&adev->dev));
+
+		clk = clk_register_gate(NULL, name, parent,
+					CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+					pdata->mmio_base + dev_desc->prv_offset,
+					31, 0, NULL);
+		parent = name;
+	}
+
 	if (dev_desc->clk_gate) {
-		clk = clk_register_gate(NULL, dev_name(&adev->dev), parent, 0,
+		clk = clk_register_gate(NULL, dev_name(&adev->dev), parent,
+					CLK_SET_RATE_PARENT,
 					pdata->mmio_base + dev_desc->prv_offset,
 					0, 0, NULL);
 		pdata->clk = clk;
-- 
2.0.0.rc0

Re: [PATCH 2/2] ACPI / LPSS: Support for fractional divider clock

[Andy Shevchenko]

On Fri, 2014-04-25 at 15:22 +0300, Heikki Krogerus wrote:
> The dividers are available for UART and SPI on both
> Lynxpoint and Baytrail. With SPI, handling the dividers is
> optional, but in case of UART they should be adjusted
> according to the requested baud rate.
> 
> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> ---
>  drivers/acpi/acpi_lpss.c | 37 ++++++++++++++++++++++++++++++-------
>  1 file changed, 30 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
> index 69e29f4..508ac9f 100644
> --- a/drivers/acpi/acpi_lpss.c
> +++ b/drivers/acpi/acpi_lpss.c
> @@ -58,6 +58,7 @@ struct lpss_device_desc {
>  	unsigned int prv_offset;
>  	size_t prv_size_override;
>  	bool clk_gate;
> +	bool clk_divider;
>  	struct lpss_shared_clock *shared_clock;
>  	void (*setup)(struct lpss_private_data *pdata);
>  };
> @@ -119,16 +120,11 @@ static struct lpss_device_desc byt_pwm_dev_desc = {
>  	.shared_clock = &pwm_clock,
>  };
>  
> -static struct lpss_shared_clock uart_clock = {
> -	.name = "uart_clk",
> -	.rate = 44236800,
> -};
> -
>  static struct lpss_device_desc byt_uart_dev_desc = {
>  	.clk_required = true,
>  	.prv_offset = 0x800,
>  	.clk_gate = true,
> -	.shared_clock = &uart_clock,
> +	.clk_divider = true,
>  	.setup = lpss_uart_setup,
>  };
>  
> @@ -246,8 +242,35 @@ static int register_device_clock(struct acpi_device *adev,
>  		parent = shared_clock->name;
>  	}
>  
> +	if (dev_desc->clk_divider) {
> +		char *name = kzalloc(strlen(dev_name(&adev->dev)) + 8,
> +				     GFP_KERNEL);
> +		if (!name)
> +			return -ENOMEM;
> +		strcpy(name, "div_clk-");
> +		strcat(name, dev_name(&adev->dev));

Just kasprintf() instead of a few LOCs?

> +
> +		clk = clk_register_fractional_divider(NULL, name, parent, 0,
> +					pdata->mmio_base + dev_desc->prv_offset,
> +					1, 15, 16, 15, 0, NULL);
> +		parent = name;
> +
> +		name = kzalloc(strlen(dev_name(&adev->dev)) + 11, GFP_KERNEL);
> +		if (!name)
> +			return -ENOMEM;
> +		strcpy(name, "clk_update-");
> +		strcat(name, dev_name(&adev->dev));

Ditto.

> +
> +		clk = clk_register_gate(NULL, name, parent,
> +					CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> +					pdata->mmio_base + dev_desc->prv_offset,
> +					31, 0, NULL);
> +		parent = name;
> +	}
> +
>  	if (dev_desc->clk_gate) {
> -		clk = clk_register_gate(NULL, dev_name(&adev->dev), parent, 0,
> +		clk = clk_register_gate(NULL, dev_name(&adev->dev), parent,
> +					CLK_SET_RATE_PARENT,
>  					pdata->mmio_base + dev_desc->prv_offset,
>  					0, 0, NULL);
>  		pdata->clk = clk;


-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 2/2] ACPI / LPSS: Support for fractional divider clock

[Heikki Krogerus]

On Fri, Apr 25, 2014 at 04:44:14PM +0300, Andy Shevchenko wrote:
> Just kasprintf() instead of a few LOCs?

Thanks Andy. I didn't even know about it :).


-- 
heikki