From: Jiang Liu <jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: Benjamin Herrenschmidt
<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Ingo Molnar <mingo-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
"H. Peter Anvin" <hpa-YMNOUZJC4hwAvxtiuMwx3w@public.gmane.org>,
"Rafael J. Wysocki" <rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
Randy Dunlap <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
Yinghai Lu <yinghai-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Borislav Petkov <bp-Gina5bIWoIWzQB+pC5nmwQ@public.gmane.org>,
Grant Likely
<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
Yingjoe Chen
<yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>,
Matthias Brugger
<matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Tony Luck <tony.luck-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
Greg Kroah-Hartman
<gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>,
x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Andrew Morton
<akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org>,
Jiang Liu <jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [Patch Part2 v5 25/31] iommu/amd: Clean up unused MSI related code
Date: Thu, 6 Nov 2014 22:20:38 +0800 [thread overview]
Message-ID: <1415283644-2559-26-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1415283644-2559-1-git-send-email-jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Now MSI interrupt has been converted to new hierarchy irqdomain
interfaces, so kill legacy MSI related code.
Signed-off-by: Jiang Liu <jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Acked-by: Joerg Roedel <jroedel-l3A5Bk7waGM@public.gmane.org>
---
drivers/iommu/amd_iommu.c | 115 +--------------------------------------------
1 file changed, 2 insertions(+), 113 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 53265d70f0b4..336d310b5b7b 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -3958,8 +3958,7 @@ out_unlock:
return table;
}
-static int alloc_irq_index(struct irq_cfg *cfg, struct irq_2_irte *irte_info,
- u16 devid, int count)
+static int alloc_irq_index(u16 devid, int count)
{
struct irq_remap_table *table;
unsigned long flags;
@@ -3985,11 +3984,6 @@ static int alloc_irq_index(struct irq_cfg *cfg, struct irq_2_irte *irte_info,
table->table[index - c + 1] = IRTE_ALLOCATED;
index -= count - 1;
-
- cfg->remapped = 1;
- irte_info->devid = devid;
- irte_info->index = index;
-
goto out;
}
}
@@ -4189,106 +4183,6 @@ static int free_irq(int irq)
return 0;
}
-static void compose_msi_msg(struct pci_dev *pdev,
- unsigned int irq, unsigned int dest,
- struct msi_msg *msg, u8 hpet_id)
-{
- struct irq_2_irte *irte_info;
- struct irq_cfg *cfg;
- union irte irte;
-
- cfg = irq_cfg(irq);
- if (!cfg)
- return;
-
- irte_info = &cfg->irq_2_irte;
-
- irte.val = 0;
- irte.fields.vector = cfg->vector;
- irte.fields.int_type = apic->irq_delivery_mode;
- irte.fields.destination = dest;
- irte.fields.dm = apic->irq_dest_mode;
- irte.fields.valid = 1;
-
- modify_irte(irte_info->devid, irte_info->index, irte);
-
- msg->address_hi = MSI_ADDR_BASE_HI;
- msg->address_lo = MSI_ADDR_BASE_LO;
- msg->data = irte_info->index;
-}
-
-static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
-{
- struct irq_cfg *cfg;
- int index;
- u16 devid;
-
- if (!pdev)
- return -EINVAL;
-
- cfg = irq_cfg(irq);
- if (!cfg)
- return -EINVAL;
-
- devid = get_device_id(&pdev->dev);
- index = alloc_irq_index(cfg, &cfg->irq_2_irte, devid, nvec);
-
- return index < 0 ? MAX_IRQS_PER_TABLE : index;
-}
-
-static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
- int index, int offset)
-{
- struct irq_2_irte *irte_info;
- struct irq_cfg *cfg;
- u16 devid;
-
- if (!pdev)
- return -EINVAL;
-
- cfg = irq_cfg(irq);
- if (!cfg)
- return -EINVAL;
-
- if (index >= MAX_IRQS_PER_TABLE)
- return 0;
-
- devid = get_device_id(&pdev->dev);
- irte_info = &cfg->irq_2_irte;
-
- cfg->remapped = 1;
- irte_info->devid = devid;
- irte_info->index = index + offset;
-
- return 0;
-}
-
-static int alloc_hpet_msi(unsigned int irq, unsigned int id)
-{
- struct irq_2_irte *irte_info;
- struct irq_cfg *cfg;
- int index, devid;
-
- cfg = irq_cfg(irq);
- if (!cfg)
- return -EINVAL;
-
- irte_info = &cfg->irq_2_irte;
- devid = get_hpet_devid(id);
- if (devid < 0)
- return devid;
-
- index = alloc_irq_index(cfg, &cfg->irq_2_irte, devid, 1);
- if (index < 0)
- return index;
-
- cfg->remapped = 1;
- irte_info->devid = devid;
- irte_info->index = index;
-
- return 0;
-}
-
static int get_devid(struct irq_alloc_info *info)
{
int devid = -1;
@@ -4365,10 +4259,6 @@ struct irq_remap_ops amd_iommu_irq_ops = {
.setup_ioapic_entry = setup_ioapic_entry,
.set_affinity = set_affinity,
.free_irq = free_irq,
- .compose_msi_msg = compose_msi_msg,
- .msi_alloc_irq = msi_alloc_irq,
- .msi_setup_irq = msi_setup_irq,
- .alloc_hpet_msi = alloc_hpet_msi,
.get_ir_irq_domain = get_ir_irq_domain,
.get_irq_domain = get_irq_domain,
};
@@ -4466,8 +4356,7 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
else
ret = -ENOMEM;
} else {
- cfg = irq_cfg(virq);
- index = alloc_irq_index(cfg, &data->irq_2_irte, devid, nr_irqs);
+ index = alloc_irq_index(devid, nr_irqs);
}
if (index < 0) {
pr_warn("Failed to allocate IRTE\n");
--
1.7.10.4
next prev parent reply other threads:[~2014-11-06 14:20 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-06 14:20 [Patch Part2 v5 00/31] Enable hierarchy irqdomian on x86 platforms Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 01/31] irqdomain: Introduce new interfaces to support hierarchy irqdomains Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 02/31] irqdomain: Do irq_find_mapping and set_type for hierarchy irqdomain in case OF Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 03/31] genirq: Introduce helper functions to support stacked irq_chip Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 04/31] genirq: Introduce irq_chip.irq_compose_msi_msg() to support stacked irqchip Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 05/31] genirq: Add IRQ_SET_MASK_OK_DONE " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 06/31] x86, irq: Save destination CPU ID in irq_cfg Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 07/31] x86, irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 08/31] x86, hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 09/31] x86, MSI: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 10/31] x86, uv: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 11/31] x86, htirq: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 12/31] x86, dmar: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 17/31] x86, hpet: Enhance HPET IRQ to support hierarchy irqdomain Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 18/31] PCI/MSI: Remove unnecessary braces around single statements Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 20/31] PCI/MSI: Kill redundant call of irq_set_msi_desc() for MSI-X interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 21/31] PCI/MSI: Enhance core to support hierarchy irqdomain Jiang Liu
2014-11-07 10:40 ` Thomas Gleixner
2014-11-09 4:26 ` Suravee Suthikulpanit
2014-11-09 7:15 ` Jiang Liu
2014-11-10 2:03 ` Suravee Suthikulpanit
2014-11-11 13:02 ` [Patch] " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 23/31] x86, irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
[not found] ` <1415283644-2559-1-git-send-email-jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2014-11-06 14:20 ` [Patch Part2 v5 13/31] x86: irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 14/31] iommu/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 15/31] iommu/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 16/31] iommu/amd: Enhance AMD " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 19/31] PCI/MSI: Simplify PCI MSI code by initializing msi_desc.nvec_used earlier Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 22/31] x86, PCI, MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 24/31] iommu/vt-d: Clean up unused MSI related code Jiang Liu
2014-11-06 14:20 ` Jiang Liu [this message]
2014-11-06 14:20 ` [Patch Part2 v5 28/31] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 26/31] x86: irq_remapping: Clean up unused MSI related code Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 27/31] x86, irq: Clean up unused MSI related code and interfaces Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 29/31] x86, irq: Use hierarchy irqdomain to manage DMAR interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 30/31] x86, htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 31/31] x86, uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
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