From: Jiang Liu <jiang.liu@linux.intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Randy Dunlap <rdunlap@infradead.org>,
Yinghai Lu <yinghai@kernel.org>, Borislav Petkov <bp@alien8.de>,
Grant Likely <grant.likely@linaro.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Yingjoe Chen <yingjoe.chen@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Yijing Wang <wangyijing@huawei.com>,
Jiang Liu <jiang.liu@linux.intel.com>,
Alexander Gordeev <agordeev@redhat.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Andrew Morton <akpm@linux-foundation.org>,
Tony Luck <tony.luck@intel.com>, Joerg Roedel <joro@8bytes.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
x86@kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [Patch] PCI/MSI: Enhance core to support hierarchy irqdomain
Date: Tue, 11 Nov 2014 21:02:18 +0800 [thread overview]
Message-ID: <1415710943-6001-1-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1415283644-2559-22-git-send-email-jiang.liu@linux.intel.com>
Enhance PCI MSI core to support hierarchy irqdomain, so the common
code could be shared among architectures.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
---
Hi Thomas,
This update fixes a possible conflict on other architectures
when they try to use the new MSI hierarchy irqdomain, as pointed out by
Suravee Suthikulanit. The main change is as below.
Regards!
Gerry
static void msi_domain_deactivate(struct irq_domain *domain,
struct irq_data *irq_data)
{
struct msi_msg msg;
+ struct msi_desc *desc = irq_data->msi_desc;
- if (!irq_data->chip_data) {
+ if (desc->irq == irq_data->irq) {
memset(&msg, 0, sizeof(msg));
__write_msi_msg(irq_data->msi_desc, &msg);
}
---
drivers/pci/Kconfig | 4 ++
drivers/pci/msi.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/msi.h | 14 ++++++
3 files changed, 151 insertions(+)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b9db0f2ce11f..022e89745f86 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -16,6 +16,10 @@ config PCI_MSI
If you don't know what to do here, say Y.
+config PCI_MSI_IRQ_DOMAIN
+ bool
+ depends on PCI_MSI && IRQ_DOMAIN_HIERARCHY
+
config PCI_DEBUG
bool "PCI Debugging"
depends on PCI && DEBUG_KERNEL
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index da181c59394b..365e969f5e8d 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -19,6 +19,7 @@
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/slab.h>
+#include <linux/irqdomain.h>
#include "pci.h"
@@ -1098,3 +1099,135 @@ int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
return nvec;
}
EXPORT_SYMBOL(pci_enable_msix_range);
+
+#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
+/*
+ * Generate a unique ID number for each possible MSI source, the ID number
+ * is only used within the irqdomain.
+ */
+static inline irq_hw_number_t
+msi_get_hwirq(struct pci_dev *dev, struct msi_desc *desc)
+{
+ return (irq_hw_number_t)desc->msi_attrib.entry_nr |
+ PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
+ (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
+}
+
+static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq = arch_msi_irq_domain_get_hwirq(arg);
+
+ if (irq_find_mapping(domain, hwirq) > 0)
+ return -EEXIST;
+
+ ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++) {
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ domain->host_data, NULL);
+ __irq_set_handler(virq + i, handle_edge_irq, 0, "edge");
+ }
+
+ return ret;
+}
+
+static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ int i;
+
+ for (i = 0; i < nr_irqs; i++) {
+ struct msi_desc *desc = irq_get_msi_desc(virq);
+
+ if (desc)
+ desc->irq = 0;
+ }
+ irq_domain_free_irqs_top(domain, virq, nr_irqs);
+}
+
+static void msi_domain_activate(struct irq_domain *domain,
+ struct irq_data *irq_data)
+{
+ struct msi_msg msg;
+ struct msi_desc *desc = irq_data->msi_desc;
+
+ /*
+ * MSI-X message is written per-IRQ.
+ * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
+ */
+ if (desc->irq == irq_data->irq) {
+ BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
+ __write_msi_msg(irq_data->msi_desc, &msg);
+ }
+}
+
+static void msi_domain_deactivate(struct irq_domain *domain,
+ struct irq_data *irq_data)
+{
+ struct msi_msg msg;
+ struct msi_desc *desc = irq_data->msi_desc;
+
+ if (desc->irq == irq_data->irq) {
+ memset(&msg, 0, sizeof(msg));
+ __write_msi_msg(irq_data->msi_desc, &msg);
+ }
+}
+
+static struct irq_domain_ops msi_domain_ops = {
+ .alloc = msi_domain_alloc,
+ .free = msi_domain_free,
+ .activate = msi_domain_activate,
+ .deactivate = msi_domain_deactivate,
+};
+
+struct irq_domain *msi_create_irq_domain(struct device_node *of_node,
+ struct irq_chip *chip,
+ struct irq_domain *parent)
+{
+ struct irq_domain *domain;
+
+ domain = irq_domain_add_tree(of_node, &msi_domain_ops, chip);
+ if (!domain)
+ return NULL;
+
+ domain->parent = parent;
+
+ return domain;
+}
+
+int msi_irq_domain_alloc_irqs(struct irq_domain *domain, int type,
+ struct pci_dev *dev, void *arg)
+{
+ int i, virq;
+ struct msi_desc *desc;
+ int node = dev_to_node(&dev->dev);
+
+ list_for_each_entry(desc, &dev->msi_list, list) {
+ arch_msi_irq_domain_set_hwirq(arg, msi_get_hwirq(dev, desc));
+ virq = irq_domain_alloc_irqs(domain, desc->nvec_used,
+ node, arg);
+ if (virq < 0) {
+ /* Special handling for pci_enable_msi_range(). */
+ if (type == PCI_CAP_ID_MSI && desc->nvec_used > 1)
+ return 1;
+ else
+ return -ENOSPC;
+ }
+ for (i = 0; i < desc->nvec_used; i++)
+ irq_set_msi_desc_off(virq, i, desc);
+ }
+
+ list_for_each_entry(desc, &dev->msi_list, list)
+ if (desc->nvec_used == 1)
+ dev_dbg(&dev->dev, "irq %d for MSI/MSI-X\n", virq);
+ else
+ dev_dbg(&dev->dev, "irq [%d-%d] for MSI/MSI-X\n",
+ virq, virq + desc->nvec_used - 1);
+
+ return 0;
+}
+#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
diff --git a/include/linux/msi.h b/include/linux/msi.h
index 44f4746d033b..662c628fc2fa 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -75,4 +75,18 @@ struct msi_chip {
void (*teardown_irq)(struct msi_chip *chip, unsigned int irq);
};
+#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
+struct irq_domain;
+struct irq_chip;
+
+struct irq_domain *msi_create_irq_domain(struct device_node *of_node,
+ struct irq_chip *chip,
+ struct irq_domain *parent);
+int msi_irq_domain_alloc_irqs(struct irq_domain *domain, int type,
+ struct pci_dev *dev, void *arg);
+
+irq_hw_number_t arch_msi_irq_domain_get_hwirq(void *arg);
+void arch_msi_irq_domain_set_hwirq(void *arg, irq_hw_number_t hwirq);
+#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
+
#endif /* LINUX_MSI_H */
--
1.7.10.4
next prev parent reply other threads:[~2014-11-11 13:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-06 14:20 [Patch Part2 v5 00/31] Enable hierarchy irqdomian on x86 platforms Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 01/31] irqdomain: Introduce new interfaces to support hierarchy irqdomains Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 02/31] irqdomain: Do irq_find_mapping and set_type for hierarchy irqdomain in case OF Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 03/31] genirq: Introduce helper functions to support stacked irq_chip Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 04/31] genirq: Introduce irq_chip.irq_compose_msi_msg() to support stacked irqchip Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 05/31] genirq: Add IRQ_SET_MASK_OK_DONE " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 06/31] x86, irq: Save destination CPU ID in irq_cfg Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 07/31] x86, irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 08/31] x86, hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 09/31] x86, MSI: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 10/31] x86, uv: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 11/31] x86, htirq: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 12/31] x86, dmar: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 17/31] x86, hpet: Enhance HPET IRQ to support hierarchy irqdomain Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 18/31] PCI/MSI: Remove unnecessary braces around single statements Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 20/31] PCI/MSI: Kill redundant call of irq_set_msi_desc() for MSI-X interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 21/31] PCI/MSI: Enhance core to support hierarchy irqdomain Jiang Liu
2014-11-07 10:40 ` Thomas Gleixner
2014-11-09 4:26 ` Suravee Suthikulpanit
2014-11-09 7:15 ` Jiang Liu
2014-11-10 2:03 ` Suravee Suthikulpanit
2014-11-11 13:02 ` Jiang Liu [this message]
2014-11-06 14:20 ` [Patch Part2 v5 23/31] x86, irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
[not found] ` <1415283644-2559-1-git-send-email-jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2014-11-06 14:20 ` [Patch Part2 v5 13/31] x86: irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 14/31] iommu/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 15/31] iommu/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 16/31] iommu/amd: Enhance AMD " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 19/31] PCI/MSI: Simplify PCI MSI code by initializing msi_desc.nvec_used earlier Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 22/31] x86, PCI, MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 24/31] iommu/vt-d: Clean up unused MSI related code Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 25/31] iommu/amd: " Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 28/31] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 26/31] x86: irq_remapping: Clean up unused MSI related code Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 27/31] x86, irq: Clean up unused MSI related code and interfaces Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 29/31] x86, irq: Use hierarchy irqdomain to manage DMAR interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 30/31] x86, htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2014-11-06 14:20 ` [Patch Part2 v5 31/31] x86, uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
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