From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Salter Subject: Re: [PATCH V3 00/21] MMCONFIG refactoring and support for ARM64 PCI hostbridge init based on ACPI Date: Thu, 14 Jan 2016 12:32:03 -0500 Message-ID: <1452792723.28109.31.camel@redhat.com> References: <1452691267-32240-1-git-send-email-tn@semihalf.com> <1452785393.28109.16.camel@redhat.com> <5697C0EB.4020404@codeaurora.org> <20160114161238.GA20706@red-moon> <1452789524.28109.24.camel@redhat.com> <20160114170723.GB20706@red-moon> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20160114170723.GB20706@red-moon> Sender: linux-pci-owner@vger.kernel.org To: Lorenzo Pieralisi Cc: Sinan Kaya , Tomasz Nowicki , bhelgaas@google.com, arnd@arndb.de, will.deacon@arm.com, catalin.marinas@arm.com, rjw@rjwysocki.net, hanjun.guo@linaro.org, jiang.liu@linux.intel.com, Stefano.Stabellini@eu.citrix.com, robert.richter@caviumnetworks.com, mw@semihalf.com, Liviu.Dudau@arm.com, ddaney@caviumnetworks.com, tglx@linutronix.de, wangyijing@huawei.com, Suravee.Suthikulpanit@amd.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, jchandra@broadcom.com, jcm@redhat.com List-Id: linux-acpi@vger.kernel.org On Thu, 2016-01-14 at 17:07 +0000, Lorenzo Pieralisi wrote: > On Thu, Jan 14, 2016 at 11:38:44AM -0500, Mark Salter wrote: >=20 > [...] >=20 > > You would lose that bet. AddressMinimum/Maximum describe the > > PCI bus addresses. >=20 > In the mainline DT (APM Mustang), the CPU physical address correspond= ing > to IO space is 0xe010000000, PCI bus address is 0x0. >=20 > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QWordIO (Re= sourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x0000000000000000, = // Granularity > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x0000000010000000, = // Range Minimum >=20 >=20 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x000000001000FFFF, = // Range Maximum > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x000000E000000000, = // Translation Offset >=20 > See above, I will get the APM specifications to countercheck. The spec won't help other than to verify that the PCIe bridge supports = a 32-bit IO address space. The firmware sets the PCI bus base @ 0x10000000 with = a CPU base address for that window @ 0xe010000000. The pci-xgene.c driver sets the= PCI bus IO base address to whatever DT tells it too. For ACPI, we have to u= se whatever the firmware set it to and described it in the ACPI table. When I looked at this a while back, neither ACPI nor PCI had anything w= hich disallowed 32-bit IO space on the PCI bus. The 16-bit limit is an x86 l= imit in the instruction set. >=20 > I agree with you we have to verify if this IO space limitation is > real or it is just an x86ism, in which case we remove that check. >=20 > Lorenzo > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x0000000000010000, = // Length > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0,, , TypeStatic) >=20 > >=20 > >=20 > > > Jiang's patch: > > >=20 > > > https://lkml.org/lkml/2015/12/16/249 > > >=20 > > > parses the IO descriptors and stores the AddressMinimum, AddressM= aximum > > > in the IO resource (with AddressTranslation as offset which must = be the > > > *CPU* physical address mapping IO), from the log above it seems t= o me in > > > AddressMinimum APM specifies the *CPU* physical address generatin= g IO > > > cycles. > > >=20 > > > All in all, I was right to fear this would happen, and I already > > > raised the point within the ACPI spec working group, ACPI IO > > > descriptors specification is ambiguous and we must agree on how > > > they have to be specified once for all. > > >=20 > > > Lorenzo > >=20