From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Masters Subject: Re: [PATCH v3 02/17] ARM64 / ACPI: Get RSDP and ACPI boot-time tables Date: Tue, 9 Sep 2014 12:44:45 -0400 (EDT) Message-ID: <1672724278.9306589.1410281085602.JavaMail.zimbra@zmail15.collab.prod.int.phx2.redhat.com> References: <1409583475-6978-1-git-send-email-hanjun.guo@linaro.org> <1409583475-6978-3-git-send-email-hanjun.guo@linaro.org> <20140909162648.GE2910@arm.com> <540F2DCF.1010104@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <540F2DCF.1010104@redhat.com> Sender: linux-kernel-owner@vger.kernel.org To: hanjun.guo@linaro.org, Catalin Marinas Cc: linux-acpi@vger.kernel.org, Randy Dunlap , Arnd Bergmann , Charles Garcia-Tobin , Lv Zheng , Lorenzo Pieralisi , Sudeep Holla , "Rafael J. Wysocki" , grant.likely@linaro.org, Will Deacon , graeme.gregory@linaro.org, Olof Johansson , Robert Richter , Daniel Lezcano , Liviu Dudau , Bjorn Helgaas , Marc Zyngier , Rob Herring , linux-kernel@vger.kernel.org, Mark Brown , linux-arm-kernel@lists.infradead.org, Mark Rutland , Robert Moore , Jason Cooper List-Id: linux-acpi@vger.kernel.org One of the ARM guys pointed out the cache issue before I had meant to send this note then. Sorry. -- Computer Architect | Sent from my #ARM Powered Mobile device On Sep 9, 2014 12:41 PM, Jon Masters wrote: > > On 09/09/2014 12:26 PM, Catalin Marinas wrote: > > On Mon, Sep 01, 2014 at 03:On 09/09/2014 12:26 PM, Catalin Marinas wrote: > On Mon, Sep 01, 2014 at 03:57:40PM +0100, Hanjun Guo wrote: >> diff --git a/arch/arm64/include/asm/acenv.h b/arch/arm64/include/asm/acenv.h >> new file mode 100644 >> index 0000000..3899ee6 >> --- /dev/null >> +++ b/arch/arm64/include/asm/acenv.h >> @@ -0,0 +1,18 @@ >> +/* >> + * ARM64 specific ACPICA environments and implementation >> + * >> + * Copyright (C) 2014, Linaro Ltd. >> + * Author: Hanjun Guo >> + * Author: Graeme Gregory >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ >> + >> +#ifndef _ASM_ACENV_H >> +#define _ASM_ACENV_H >> + >> +#define ACPI_FLUSH_CPU_CACHE() WARN_ONCE(1, "Not currently supported on ARM64") > > Does this mean that it will be supported at some point? Looking at the > places where this function is called, I don't really see how this would > ever work on ARM. Which means that we add such macro just to be able to > compile code that would never be used on arm64. I would rather see the > relevant ACPI files only compiled on x86/IA-64 rather than arm64. That specific cache behavior is a part of e.g. ACPI C3 state support (e.g. ACPI5.1 8.1.4 Processor Power State C3). As you note, it's not going to work on 64-bit ARM as it does on x86, but it's optional to implement C3 and early 64-bit ARM systems should not report Wbindv flags in the FADT anyway. They can also set FADT.P_LVL3_LAT > 1000, which has the effect of disabling C3 support, while also allowing for use of _CST objects to define more flexible C-States later on. Jon.