[PATCH v1 00/26] ACPICA: ACPICA 20251212

[PATCH v1 00/26] ACPICA: ACPICA 20251212

[Rafael J. Wysocki]

Hi All,

This series of patches represents upstream ACPICA changes made between
the 20250807 release and the 20251212 release that have not been included
into the Linux source code yet, and some upstream ACPICA changes made after
the 20251212 release.

It contains the following material:

Alexey Simakov (1):
      ACPICA: Fix NULL pointer dereference in acpi_ev_address_space_dispatch()

Armin Wolf (5):
      ACPICA: Add UUID for Microsoft fan extensions
      ACPICA: Add UUIDs associated with TPM 2.0 devices
      ACPICA: Add support for the Microsoft display mux _OSI string
      ACPICA: Abort AML bytecode execution when executing AML_FATAL_OP
      ACPICA: Fix asltests using the Fatal() opcode

Ben Horgan (1):
      ACPICA: ACPI 6.4: PPTT: include all fields in subtable type 1

Dave Jiang (1):
      ACPICA: Add KEYP table definition

Jose Marinho (2):
      ACPICA: Add GICv5 MADT structures
      ACPICA: Add Arm IORT IWB node definitions

Michal Camacho Romero (10):
      ACPICA: Add support for the new ACPI Table: DTPR
      ACPICA: Add DTPR table support for the ASL compiler
      ACPICA: Define DTPR structure related info tables and data template
      ACPICA: Create auxiliary ACPI_TPR_AUX_SR structure for iASL compiler
      ACPICA: Fix Segmentation Fault error related to DTPR
      ACPICA: Verify DTPR and TPR Instance buffer pointers
      ACPICA: Cleanup comments and DTPR Table handle functions
      ACPICA: Align comments in TPRn-related structures
      ACPICA: Replace TPRn Base and Limit registers
      ACPICA: Refactor for TPR Base/Limit registers bitmasks

Pawel Chmielewski (3):
      ACPICA: actbl2.h: ACPI 6.6: RAS2: Update Parameter Block structure
      ACPICA: actbl3.h: ACPI 6.6: SRAT: New flag in Memory Affinity Structure
      ACPICA: ACPI 6.6: Add _VDM (Voltage Domain) object

Saket Dumbre (1):
      ACPICA: Logfile: Changes for version 20251212

Xianglai Li (1):
      ACPICA: iASL: Add definitions for the IOVT table

Zilin Guan (1):
      ACPICA: ACPICA: replace ACPI_FREE() with acpi_ut_delete_object_desc()



Thanks!

[PATCH v1 01/26] ACPICA: Add support for the new ACPI Table: DTPR

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Define a new the ACPI Table, structure and registers, related with it, according
to the latest version of the Intel TXT DMA Protection Ranges (TPR) specification
(Revision 0.73):

*    DTPR ACPI Table
*    TPR Base Register
*    TPR Serialize Request Register
*    TPR Limit Register
*    TPR Instance Structure
*    DMAR TXT Protected Reporting Structure

These structures will be used to handle TPRs on the Intel CPU's.

Link: https://github.com/acpica/acpica/commit/10e7a88f70da
Link: https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Protection_Ranges_rev_0p73.pdf
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 86 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 7f35eb0e8458..23449a068c5c 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -47,6 +47,7 @@
 #define ACPI_SIG_HPET           "HPET"	/* High Precision Event Timer table */
 #define ACPI_SIG_IBFT           "IBFT"	/* iSCSI Boot Firmware Table */
 #define ACPI_SIG_MSCT           "MSCT"	/* Maximum System Characteristics Table */
+#define ACPI_SIG_DTPR           "DTPR"	/* TXT DMA Protection Ranges reporting table */
 
 #define ACPI_SIG_S3PT           "S3PT"	/* S3 Performance (sub)Table */
 #define ACPI_SIG_PCCS           "PCC"	/* PCC Shared Memory Region */
@@ -1973,6 +1974,91 @@ struct acpi_ibft_target {
 	u16 reverse_chap_secret_offset;
 };
 
+/*******************************************************************************
+ *
+ * DTPR - DMA TPR Reporting
+ *        Version 1
+ *
+ * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection
+ *              Ranges",
+ * Revision 0.73, August 2021
+ *
+ ******************************************************************************/
+
+struct acpi_table_dtpr {
+	struct acpi_table_header header;
+	u32 flags;		// 36
+};
+
+struct acpi_tpr_array {
+	u64 base;
+};
+
+struct acpi_dtpr_instance {
+	u32 flags;
+	u32 tpr_cnt;
+	struct acpi_tpr_array tpr_array[];
+};
+
+/*******************************************************************************
+ * TPRn_BASE
+ *
+ * Specifies the start address of TPRn region. TPR region address and size must
+ * be with 1MB resolution. These bits are compared with the result of the
+ * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an
+ * access fall within the TPRn defined region.
+*******************************************************************************/
+struct acpi_dtprn_base_reg {
+	u64 reserved0:3;
+	u64 rw:1;		// access: 1 == RO, 0 == RW (for TPR must be RW)
+	u64 enable:1;		// 0 == range enabled, 1 == range disabled
+	u64 reserved1:15;
+	u64 tpr_base_rw:44;	// minimal TPrn_base resolution is 1MB.
+	// applied to the incoming address, to determine if an
+	// access fall within the TPrn defined region.
+	// width is determined by a bus width which can be
+	// obtainedvia CPUID function 0x80000008.
+	//u64 unused : 1;
+};
+
+/*******************************************************************************
+ * TPRn_LIMIT
+ *
+ * This register defines an isolated region of memory that can be enabled
+ * to prohibit certain system agents from accessing memory. When an agent
+ * sends a request upstream, whether snooped or not, a TPR prevents that
+ * transaction from changing the state of memory.
+*******************************************************************************/
+
+struct acpi_dtprn_limit_reg {
+	u64 reserved0:3;
+	u64 rw:1;		// access: 1 == RO, 0 == RW (for TPR must be RW)
+	u64 enable:1;		// 0 == range enabled, 1 == range disabled
+	u64 reserved1:15;
+	u64 tpr_limit_rw:44;	// minimal TPrn_limit resolution is 1MB.
+	// these bits define TPR limit address.
+	// width is determined by a bus width.
+
+	//u64 unused : 1;
+};
+
+/*******************************************************************************
+ * SERIALIZE_REQUEST
+ *
+ * This register is used to request serialization of non-coherent DMA
+ * transactions. OS shall  issue it before changing of TPR settings
+ * (base / size).
+*******************************************************************************/
+
+struct acpi_tpr_serialize_request {
+	u64 sts:1;		// status of serialization request (RO)
+	// 0 == register idle, 1 == serialization in progress
+	u64 ctrl:1;		// control field to initiate serialization (RW)
+	// 0 == normal, 1 == initialize serialization
+	// (self-clear to allow multiple serialization requests)
+	u64 unused:62;
+};
+
 /* Reset to default packing */
 
 #pragma pack()
-- 
2.51.0

[PATCH v1 02/26] ACPICA: ACPICA: replace ACPI_FREE() with acpi_ut_delete_object_desc()

[Rafael J. Wysocki]

From: Zilin Guan <zilin@seu.edu.cn>

acpi_ut_create_internal_object() may allocate memory from a slab cache
via kmem_cache_zalloc(), but the code currently frees it with ACPI_FREE(),
which calls kfree().

This mismatch prevents the object from being released properly and may
lead to memory leaks or other issues.

Fix this by replacing ACPI_FREE() with acpi_ut_delete_object_desc(),
which matches the allocation method used for internal objects.

Link: https://github.com/acpica/acpica/commit/a1c55dfea194
Signed-off-by: Zilin Guan <zilin@seu.edu.cn>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpica/nsxfname.c | 2 +-
 drivers/acpi/acpica/utobject.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/acpica/nsxfname.c b/drivers/acpi/acpica/nsxfname.c
index 1db831545ec8..b6895a48ae68 100644
--- a/drivers/acpi/acpica/nsxfname.c
+++ b/drivers/acpi/acpica/nsxfname.c
@@ -601,7 +601,7 @@ acpi_status acpi_install_method(u8 *buffer)
 error_exit:
 
 	ACPI_FREE(aml_buffer);
-	ACPI_FREE(method_obj);
+	acpi_ut_delete_object_desc(method_obj);
 	return (status);
 }
 ACPI_EXPORT_SYMBOL(acpi_install_method)
diff --git a/drivers/acpi/acpica/utobject.c b/drivers/acpi/acpica/utobject.c
index 272e46208263..8362204b57b5 100644
--- a/drivers/acpi/acpica/utobject.c
+++ b/drivers/acpi/acpica/utobject.c
@@ -148,7 +148,7 @@ union acpi_operand_object *acpi_ut_create_package_object(u32 count)
 	package_elements = ACPI_ALLOCATE_ZEROED(((acpi_size)count +
 						 1) * sizeof(void *));
 	if (!package_elements) {
-		ACPI_FREE(package_desc);
+		acpi_ut_delete_object_desc(package_desc);
 		return_PTR(NULL);
 	}
 
-- 
2.51.0

[PATCH v1 03/26] ACPICA: Add UUID for Microsoft fan extensions

[Rafael J. Wysocki]

From: Armin Wolf <W_Armin@gmx.de>

Microsoft has designed an interface for reading/writing fan speed
trip points. Add the associated UUID to the list of known UUIDs so
that the ASL compiler stops complaining about it.

Link: https://github.com/acpica/acpica/commit/67f0202c0fb4
Signed-off-by: Armin Wolf <W_Armin@gmx.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/acuuid.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/acpi/acuuid.h b/include/acpi/acuuid.h
index 25dd3e998727..0eda9d997f31 100644
--- a/include/acpi/acuuid.h
+++ b/include/acpi/acuuid.h
@@ -71,4 +71,5 @@
 #define UUID_USB4_CAPABILITIES          "23a0d13a-26ab-486c-9c5f-0ffa525a575a"
 #define UUID_1ST_FUNCTION_ID            "893f00a6-660c-494e-bcfd-3043f4fb67c0"
 #define UUID_2ND_FUNCTION_ID            "107ededd-d381-4fd7-8da9-08e9a6c79644"
+#define UUID_FAN_TRIP_POINTS            "a7611840-99fe-41ae-a488-35c75926c8eb"
 #endif				/* __ACUUID_H__ */
-- 
2.51.0

[PATCH v1 04/26] ACPICA: Add UUIDs associated with TPM 2.0 devices

[Rafael J. Wysocki]

From: Armin Wolf <W_Armin@gmx.de>

The Trusted Computing Group has designed multiple interface extensions
around TPM 2.0 devices including the ACPI start method, hardware
information and memory clear features. Add the associated UUIDs to the
list of known UUIDs so that the ASL compiler stops complaining about
them.

Link: https://github.com/acpica/acpica/commit/0e8b10b05825
Signed-off-by: Armin Wolf <W_Armin@gmx.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/acuuid.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/acpi/acuuid.h b/include/acpi/acuuid.h
index 0eda9d997f31..b2e29da6ba0a 100644
--- a/include/acpi/acuuid.h
+++ b/include/acpi/acuuid.h
@@ -37,6 +37,11 @@
 #define UUID_DEVICE_LABELING            "e5c937d0-3553-4d7a-9117-ea4d19c3434d"
 #define UUID_PHYSICAL_PRESENCE          "3dddfaa6-361b-4eb4-a424-8d10089d1653"
 
+/* TPM */
+#define UUID_HARDWARE_INFORMATION       "cf8e16a5-c1e8-4e25-b712-4f54a96702c8"
+#define UUID_START_METHOD               "6bbf6cab-5463-4714-b7cd-f0203c0368d4"
+#define UUID_MEMORY_CLEAR               "376054ed-cc13-4675-901c-4756d7f2d45d"
+
 /* NVDIMM - NFIT table */
 
 #define UUID_NFIT_DIMM                  "4309ac30-0d11-11e4-9191-0800200c9a66"
-- 
2.51.0

[PATCH v1 05/26] ACPICA: Fix NULL pointer dereference in acpi_ev_address_space_dispatch()

[Rafael J. Wysocki]

From: Alexey Simakov <bigalex934@gmail.com>

Cover a missed execution path with a new check.

Fixes: 0acf24ad7e10 ("ACPICA: Add support for PCC Opregion special context data")
Link: https://github.com/acpica/acpica/commit/f421dd9dd897
Signed-off-by: Alexey Simakov <bigalex934@gmail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpica/evregion.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/acpica/evregion.c b/drivers/acpi/acpica/evregion.c
index fa3475da7ea9..b6198f73c81d 100644
--- a/drivers/acpi/acpica/evregion.c
+++ b/drivers/acpi/acpica/evregion.c
@@ -163,7 +163,9 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 			return_ACPI_STATUS(AE_NOT_EXIST);
 		}
 
-		if (region_obj->region.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+		if (field_obj
+		    && region_obj->region.space_id ==
+		    ACPI_ADR_SPACE_PLATFORM_COMM) {
 			struct acpi_pcc_info *ctx =
 			    handler_desc->address_space.context;
 
-- 
2.51.0

Re: [PATCH v1 05/26] ACPICA: Fix NULL pointer dereference in acpi_ev_address_space_dispatch()

[Guenter Roeck]

Hi,

On Wed, Jan 14, 2026 at 01:20:17PM +0100, Rafael J. Wysocki wrote:
> From: Alexey Simakov <bigalex934@gmail.com>
> 
> Cover a missed execution path with a new check.
> 
> Fixes: 0acf24ad7e10 ("ACPICA: Add support for PCC Opregion special context data")
> Link: https://github.com/acpica/acpica/commit/f421dd9dd897
> Signed-off-by: Alexey Simakov <bigalex934@gmail.com>
> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
>  drivers/acpi/acpica/evregion.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/acpi/acpica/evregion.c b/drivers/acpi/acpica/evregion.c
> index fa3475da7ea9..b6198f73c81d 100644
> --- a/drivers/acpi/acpica/evregion.c
> +++ b/drivers/acpi/acpica/evregion.c
> @@ -163,7 +163,9 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
>  			return_ACPI_STATUS(AE_NOT_EXIST);
>  		}
>  
> -		if (region_obj->region.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
> +		if (field_obj
> +		    && region_obj->region.space_id ==
> +		    ACPI_ADR_SPACE_PLATFORM_COMM) {
>  			struct acpi_pcc_info *ctx =
>  			    handler_desc->address_space.context;
>  
Google's experimental AI review agent provided the following feedback:

 If this setup block is executed with a NULL `field_obj`, it will skip
 initializing `ctx->length` and `ctx->subspace_id` even though they do not
 depend on `field_obj`.

 Additionally, because this initialization is part of the
 `!(region_obj->region.flags & AOPOBJ_SETUP_COMPLETE)` block, the setup flag
 will be set shortly after this. Does this mean that if the first call has a
 NULL `field_obj`, the region will be marked as setup complete, and a
 subsequent call with a valid `field_obj` will never initialize
 `ctx->internal_buffer`? Should the `field_obj` check only guard the
 assignment of `ctx->internal_buffer`?

Please let me know if this is a real concern or not to help improve the agent.

Thanks,
Guenter

Re: [PATCH v1 05/26] ACPICA: Fix NULL pointer dereference in acpi_ev_address_space_dispatch()

[Rafael J. Wysocki]

On Mon, Mar 16, 2026 at 6:46 PM Guenter Roeck <linux@roeck-us.net> wrote:
>
> Hi,
>
> On Wed, Jan 14, 2026 at 01:20:17PM +0100, Rafael J. Wysocki wrote:
> > From: Alexey Simakov <bigalex934@gmail.com>
> >
> > Cover a missed execution path with a new check.
> >
> > Fixes: 0acf24ad7e10 ("ACPICA: Add support for PCC Opregion special context data")
> > Link: https://github.com/acpica/acpica/commit/f421dd9dd897
> > Signed-off-by: Alexey Simakov <bigalex934@gmail.com>
> > Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> > ---
> >  drivers/acpi/acpica/evregion.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/acpi/acpica/evregion.c b/drivers/acpi/acpica/evregion.c
> > index fa3475da7ea9..b6198f73c81d 100644
> > --- a/drivers/acpi/acpica/evregion.c
> > +++ b/drivers/acpi/acpica/evregion.c
> > @@ -163,7 +163,9 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
> >                       return_ACPI_STATUS(AE_NOT_EXIST);
> >               }
> >
> > -             if (region_obj->region.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
> > +             if (field_obj
> > +                 && region_obj->region.space_id ==
> > +                 ACPI_ADR_SPACE_PLATFORM_COMM) {
> >                       struct acpi_pcc_info *ctx =
> >                           handler_desc->address_space.context;
> >
> Google's experimental AI review agent provided the following feedback:
>
>  If this setup block is executed with a NULL `field_obj`, it will skip
>  initializing `ctx->length` and `ctx->subspace_id` even though they do not
>  depend on `field_obj`.
>
>  Additionally, because this initialization is part of the
>  `!(region_obj->region.flags & AOPOBJ_SETUP_COMPLETE)` block, the setup flag
>  will be set shortly after this. Does this mean that if the first call has a
>  NULL `field_obj`, the region will be marked as setup complete, and a
>  subsequent call with a valid `field_obj` will never initialize
>  `ctx->internal_buffer`? Should the `field_obj` check only guard the
>  assignment of `ctx->internal_buffer`?

Thanks for the report!

> Please let me know if this is a real concern or not to help improve the agent.

Saket, Pawel, can you please have a look at this?

Re: [PATCH v1 05/26] ACPICA: Fix NULL pointer dereference in acpi_ev_address_space_dispatch()

[Guenter Roeck]

Hi,

On 3/23/26 16:26, Dumbre, Saket wrote:
> Hi Guenter,
> 
> Yes, the experimental AI is spot-on in this case (although this is a very rare corner case path)! Internal buffer can stay uninitialized when field object is NULL (in case of loading ACPI tables from memory, doesn't target the PCC region though, if anything maybe just the PCCT table? The flow gets really complex to track each individual ACPI table), but otherwise, the other 2 fields shouldn't depend to be initialized on the existence of field object. The easiest fix would be to have a nested inner if (field_obj) {.....initialize ctx->internal_buffer....} and unlink the dependency on field_obj not being NULL on the remaining 2 ctx initializations. Thanks a lot for bringing this up and please feel free to submit a PR for ACPICA (and get the credit you deserve) which will then be pipelined into a patch for the Linux kernel when Rafael picks up the new ACPICA release commits! If you can deploy the experimental (or better yet, the release product) AI to find more bugs like this 
> and confirm after a human review if they are indeed real or not, that would help make ACPICA a lot better!
> 

My knowledge about ACPI code and ACPI patch submission rules is just about zero.
I'll be happy to submit patches into the Linux kernel, but I don't think I'll have
the time to learn how to submit patches into ACPI, sorry.

Guenter

[PATCH v1 06/26] ACPICA: Add KEYP table definition

[Rafael J. Wysocki]

From: Dave Jiang <dave.jiang@intel.com>

Software uses this table to discover the base address of the Key
Configuration Unit (KCU) register block associated with each IDE capable
host bridge.

[1]: Root Complex IDE Key Configuration Unit Software Programming Guide
     https://cdrdv2.intel.com/v1/dl/getContent/732838

Link: https://github.com/acpica/acpica/commit/af970172e2dd
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl2.h | 59 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index f726bce3eb84..4040e4df051b 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -32,6 +32,7 @@
 #define ACPI_SIG_ERDT           "ERDT"	/* Enhanced Resource Director Technology */
 #define ACPI_SIG_IORT           "IORT"	/* IO Remapping Table */
 #define ACPI_SIG_IVRS           "IVRS"	/* I/O Virtualization Reporting Structure */
+#define ACPI_SIG_KEYP           "KEYP"	/* Key Programming Interface for IDE */
 #define ACPI_SIG_LPIT           "LPIT"	/* Low Power Idle Table */
 #define ACPI_SIG_MADT           "APIC"	/* Multiple APIC Description Table */
 #define ACPI_SIG_MCFG           "MCFG"	/* PCI Memory Mapped Configuration table */
@@ -1065,6 +1066,64 @@ struct acpi_ivrs_memory {
 	u64 memory_length;
 };
 
+/*******************************************************************************
+ *
+ * KEYP - Key Programming Interface for Root Complex Integrity and Data
+ *        Encryption (IDE)
+ *        Version 1
+ *
+ * Conforms to "Key Programming Interface for Root Complex Integrity and Data
+ * Encryption (IDE)" document. See under ACPI-Related Documents.
+ *
+ ******************************************************************************/
+struct acpi_table_keyp {
+	struct acpi_table_header header;	/* Common ACPI table header */
+	u32 reserved;
+};
+
+/* KEYP common subtable header */
+
+struct acpi_keyp_common_header {
+	u8 type;
+	u8 reserved;
+	u16 length;
+};
+
+/* Values for Type field above */
+
+enum acpi_keyp_type {
+	ACPI_KEYP_TYPE_CONFIG_UNIT = 0,
+};
+
+/* Root Port Information Structure */
+
+struct acpi_keyp_rp_info {
+	u16 segment;
+	u8 bus;
+	u8 devfn;
+};
+
+/* Key Configuration Unit Structure */
+
+struct acpi_keyp_config_unit {
+	struct acpi_keyp_common_header header;
+	u8 protocol_type;
+	u8 version;
+	u8 root_port_count;
+	u8 flags;
+	u64 register_base_address;
+	struct acpi_keyp_rp_info rp_info[];
+};
+
+enum acpi_keyp_protocol_type {
+	ACPI_KEYP_PROTO_TYPE_INVALID = 0,
+	ACPI_KEYP_PROTO_TYPE_PCIE,
+	ACPI_KEYP_PROTO_TYPE_CXL,
+	ACPI_KEYP_PROTO_TYPE_RESERVED
+};
+
+#define ACPI_KEYP_F_TVM_USABLE      (1)
+
 /*******************************************************************************
  *
  * LPIT - Low Power Idle Table
-- 
2.51.0

[PATCH v1 07/26] ACPICA: Add support for the Microsoft display mux _OSI string

[Rafael J. Wysocki]

From: Armin Wolf <W_Armin@gmx.de>

As per [1].

Link: https://learn.microsoft.com/en-us/windows-hardware/drivers/display/automatic-display-switch [1]
Link: https://github.com/acpica/acpica/commit/28b644211ff2
Signed-off-by: Armin Wolf <W_Armin@gmx.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpica/utosi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/acpica/utosi.c b/drivers/acpi/acpica/utosi.c
index f6ac16729e42..88d04183ad0a 100644
--- a/drivers/acpi/acpica/utosi.c
+++ b/drivers/acpi/acpica/utosi.c
@@ -92,7 +92,11 @@ static struct acpi_interface_info acpi_default_supported_interfaces[] = {
 	{"Processor Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
 	{"3.0 Thermal Model", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
 	{"3.0 _SCP Extensions", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
-	{"Processor Aggregator Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0}
+	{"Processor Aggregator Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
+
+	/* See https://learn.microsoft.com/en-us/windows-hardware/drivers/display/automatic-display-switch */
+
+	{"DisplayMux", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0}
 };
 
 /*******************************************************************************
-- 
2.51.0

[PATCH v1 08/26] ACPICA: iASL: Add definitions for the IOVT table

[Rafael J. Wysocki]

From: Xianglai Li <lixianglai@loongson.cn>

Add definitions for the IOVT table and its subtables.

Link: https://github.com/acpica/acpica/commit/14c0def532ac
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl2.h | 68 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 4040e4df051b..617be4bd3d4a 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -31,6 +31,7 @@
 #define ACPI_SIG_CDAT           "CDAT"	/* Coherent Device Attribute Table */
 #define ACPI_SIG_ERDT           "ERDT"	/* Enhanced Resource Director Technology */
 #define ACPI_SIG_IORT           "IORT"	/* IO Remapping Table */
+#define ACPI_SIG_IOVT           "IOVT"	/* I/O Virtualization Table */
 #define ACPI_SIG_IVRS           "IVRS"	/* I/O Virtualization Reporting Structure */
 #define ACPI_SIG_KEYP           "KEYP"	/* Key Programming Interface for IDE */
 #define ACPI_SIG_LPIT           "LPIT"	/* Low Power Idle Table */
@@ -859,6 +860,73 @@ struct acpi_iort_rmr_desc {
 	u32 reserved;
 };
 
+/*******************************************************************************
+ *
+ * IOVT - I/O Virtualization Table
+ *
+ * Conforms to "LoongArch I/O Virtualization Table",
+ *        Version 0.1, October 2024
+ *
+ ******************************************************************************/
+
+struct acpi_table_iovt {
+	struct acpi_table_header header;	/* Common ACPI table header */
+	u16 iommu_count;
+	u16 iommu_offset;
+	u8 reserved[8];
+};
+
+/* IOVT subtable header */
+
+struct acpi_iovt_header {
+	u16 type;
+	u16 length;
+};
+
+/* Values for Type field above */
+
+enum acpi_iovt_iommu_type {
+	ACPI_IOVT_IOMMU_V1 = 0x00,
+	ACPI_IOVT_IOMMU_RESERVED = 0x01	/* 1 and greater are reserved */
+};
+
+/* IOVT subtables */
+
+struct acpi_iovt_iommu {
+	struct acpi_iovt_header header;
+	u32 flags;
+	u16 segment;
+	u16 phy_width;		/* Physical Address Width */
+	u16 virt_width;		/* Virtual Address Width */
+	u16 max_page_level;
+	u64 page_size;
+	u32 device_id;
+	u64 base_address;
+	u32 address_space_size;
+	u8 interrupt_type;
+	u8 reserved[3];
+	u32 gsi_number;
+	u32 proximity_domain;
+	u32 max_device_num;
+	u32 device_entry_num;
+	u32 device_entry_offset;
+};
+
+struct acpi_iovt_device_entry {
+	u8 type;
+	u8 length;
+	u8 flags;
+	u8 reserved[3];
+	u16 device_id;
+};
+
+enum acpi_iovt_device_entry_type {
+	ACPI_IOVT_DEVICE_ENTRY_SINGLE = 0x00,
+	ACPI_IOVT_DEVICE_ENTRY_START = 0x01,
+	ACPI_IOVT_DEVICE_ENTRY_END = 0x02,
+	ACPI_IOVT_DEVICE_ENTRY_RESERVED = 0x03	/* 3 and greater are reserved */
+};
+
 /*******************************************************************************
  *
  * IVRS - I/O Virtualization Reporting Structure
-- 
2.51.0

[PATCH v1 09/26] ACPICA: Add DTPR table support for the ASL compiler

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Define DTPR related structures offsets.

Link: https://github.com/acpica/acpica/commit/c6fc16c8936d
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 23449a068c5c..423e7232974a 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -37,6 +37,7 @@
 #define ACPI_SIG_DBGP           "DBGP"	/* Debug Port table */
 #define ACPI_SIG_DMAR           "DMAR"	/* DMA Remapping table */
 #define ACPI_SIG_DRTM           "DRTM"	/* Dynamic Root of Trust for Measurement table */
+#define ACPI_SIG_DTPR           "DTPR"	/* DMA TXT Protection Ranges table */
 #define ACPI_SIG_ECDT           "ECDT"	/* Embedded Controller Boot Resources Table */
 #define ACPI_SIG_EINJ           "EINJ"	/* Error Injection table */
 #define ACPI_SIG_ERST           "ERST"	/* Error Record Serialization Table */
@@ -47,7 +48,6 @@
 #define ACPI_SIG_HPET           "HPET"	/* High Precision Event Timer table */
 #define ACPI_SIG_IBFT           "IBFT"	/* iSCSI Boot Firmware Table */
 #define ACPI_SIG_MSCT           "MSCT"	/* Maximum System Characteristics Table */
-#define ACPI_SIG_DTPR           "DTPR"	/* TXT DMA Protection Ranges reporting table */
 
 #define ACPI_SIG_S3PT           "S3PT"	/* S3 Performance (sub)Table */
 #define ACPI_SIG_PCCS           "PCC"	/* PCC Shared Memory Region */
@@ -1994,7 +1994,7 @@ struct acpi_tpr_array {
 	u64 base;
 };
 
-struct acpi_dtpr_instance {
+struct acpi_tpr_instance {
 	u32 flags;
 	u32 tpr_cnt;
 	struct acpi_tpr_array tpr_array[];
@@ -2008,7 +2008,7 @@ struct acpi_dtpr_instance {
  * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an
  * access fall within the TPRn defined region.
 *******************************************************************************/
-struct acpi_dtprn_base_reg {
+struct acpi_tprn_base_reg {
 	u64 reserved0:3;
 	u64 rw:1;		// access: 1 == RO, 0 == RW (for TPR must be RW)
 	u64 enable:1;		// 0 == range enabled, 1 == range disabled
@@ -2030,7 +2030,7 @@ struct acpi_dtprn_base_reg {
  * transaction from changing the state of memory.
 *******************************************************************************/
 
-struct acpi_dtprn_limit_reg {
+struct acpi_tprn_limit_reg {
 	u64 reserved0:3;
 	u64 rw:1;		// access: 1 == RO, 0 == RW (for TPR must be RW)
 	u64 enable:1;		// 0 == range enabled, 1 == range disabled
-- 
2.51.0

[PATCH v1 10/26] ACPICA: Define DTPR structure related info tables and data template

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

 * DTPR Table Info
 * TPR Instance Table Info
 * TPR Array Table Info
 * TPR Serialize Request Table Info
 * DTPR Table Data Template

Link: https://github.com/acpica/acpica/commit/abadf1d34732
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 423e7232974a..f16020829f42 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -1976,7 +1976,7 @@ struct acpi_ibft_target {
 
 /*******************************************************************************
  *
- * DTPR - DMA TPR Reporting
+ * DTPR - DMA TXT Protection Ranges Table
  *        Version 1
  *
  * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection
@@ -1988,6 +1988,7 @@ struct acpi_ibft_target {
 struct acpi_table_dtpr {
 	struct acpi_table_header header;
 	u32 flags;		// 36
+	u32 ins_cnt;
 };
 
 struct acpi_tpr_array {
-- 
2.51.0

[PATCH v1 11/26] ACPICA: Abort AML bytecode execution when executing AML_FATAL_OP

[Rafael J. Wysocki]

From: Armin Wolf <W_Armin@gmx.de>

The ACPI specification states that when executing AML_FATAL_OP,
the OS should log the fatal error event and shutdown in a timely
fashion.

Windows complies with this requirement by immediatly entering a
Bso_d, effectively aborting the execution of the AML bytecode in
question.

ACPICA however might continue with the AML bytecode execution
should acpi_os_signal() simply return AE_OK. This will cause issues
because ACPI BIOS implementations might assume that the Fatal()
operator does not return.

Fix this by aborting the AML bytecode execution in such a case
by returning AE_ERROR. Also turn struct acpi_signal_fatal_info into a
local variable because of its small size (12 bytes) and to ensure
that acpi_os_signal() always receives valid information about the
fatal ACPI BIOS error.

Link: https://github.com/acpica/acpica/commit/d516c7758ba6
Signed-off-by: Armin Wolf <W_Armin@gmx.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpica/exoparg3.c | 46 +++++++++++++---------------------
 1 file changed, 18 insertions(+), 28 deletions(-)

diff --git a/drivers/acpi/acpica/exoparg3.c b/drivers/acpi/acpica/exoparg3.c
index bf08110ed6d2..c8c8c4e49563 100644
--- a/drivers/acpi/acpica/exoparg3.c
+++ b/drivers/acpi/acpica/exoparg3.c
@@ -10,6 +10,7 @@
 #include <acpi/acpi.h>
 #include "accommon.h"
 #include "acinterp.h"
+#include <acpi/acoutput.h>
 #include "acparser.h"
 #include "amlcode.h"
 
@@ -51,8 +52,7 @@ ACPI_MODULE_NAME("exoparg3")
 acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
 {
 	union acpi_operand_object **operand = &walk_state->operands[0];
-	struct acpi_signal_fatal_info *fatal;
-	acpi_status status = AE_OK;
+	struct acpi_signal_fatal_info fatal;
 
 	ACPI_FUNCTION_TRACE_STR(ex_opcode_3A_0T_0R,
 				acpi_ps_get_opcode_name(walk_state->opcode));
@@ -60,28 +60,23 @@ acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
 	switch (walk_state->opcode) {
 	case AML_FATAL_OP:	/* Fatal (fatal_type fatal_code fatal_arg) */
 
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "FatalOp: Type %X Code %X Arg %X "
-				  "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n",
-				  (u32)operand[0]->integer.value,
-				  (u32)operand[1]->integer.value,
-				  (u32)operand[2]->integer.value));
-
-		fatal = ACPI_ALLOCATE(sizeof(struct acpi_signal_fatal_info));
-		if (fatal) {
-			fatal->type = (u32) operand[0]->integer.value;
-			fatal->code = (u32) operand[1]->integer.value;
-			fatal->argument = (u32) operand[2]->integer.value;
-		}
+		fatal.type = (u32)operand[0]->integer.value;
+		fatal.code = (u32)operand[1]->integer.value;
+		fatal.argument = (u32)operand[2]->integer.value;
 
-		/* Always signal the OS! */
+		ACPI_BIOS_ERROR((AE_INFO,
+				 "Fatal ACPI BIOS error (Type 0x%X Code 0x%X Arg 0x%X)\n",
+				 fatal.type, fatal.code, fatal.argument));
 
-		status = acpi_os_signal(ACPI_SIGNAL_FATAL, fatal);
+		/* Always signal the OS! */
 
-		/* Might return while OS is shutting down, just continue */
+		acpi_os_signal(ACPI_SIGNAL_FATAL, &fatal);
 
-		ACPI_FREE(fatal);
-		goto cleanup;
+		/*
+		 * Might return while OS is shutting down, so abort the AML execution
+		 * by returning an error.
+		 */
+		return_ACPI_STATUS(AE_ERROR);
 
 	case AML_EXTERNAL_OP:
 		/*
@@ -93,21 +88,16 @@ acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
 		 * wrong if an external opcode ever gets here.
 		 */
 		ACPI_ERROR((AE_INFO, "Executed External Op"));
-		status = AE_OK;
-		goto cleanup;
+
+		return_ACPI_STATUS(AE_OK);
 
 	default:
 
 		ACPI_ERROR((AE_INFO, "Unknown AML opcode 0x%X",
 			    walk_state->opcode));
 
-		status = AE_AML_BAD_OPCODE;
-		goto cleanup;
+		return_ACPI_STATUS(AE_AML_BAD_OPCODE);
 	}
-
-cleanup:
-
-	return_ACPI_STATUS(status);
 }
 
 /*******************************************************************************
-- 
2.51.0

[PATCH v1 12/26] ACPICA: ACPI 6.4: PPTT: include all fields in subtable type1

[Rafael J. Wysocki]

From: Ben Horgan <ben.horgan@arm.com>

In PPTT version 3 an extra field, Cache ID, was added to the Cache Type
Structure.  The struct, struct acpi_pptt_cache_v1, contains only this field. This
differs from the treatment of other versioned structures and is unexpected
for linux which reuses the actbl2.h header file. Include all the fields of
the new Cache Type Structure in struct acpi_pptt_cache_v1 and fix up all uses.

Link: https://github.com/acpica/acpica/commit/a9ec9105f552
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl2.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 617be4bd3d4a..15856ae8b1e1 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -2953,6 +2953,15 @@ struct acpi_pptt_cache {
 /* 1: Cache Type Structure for PPTT version 3 */
 
 struct acpi_pptt_cache_v1 {
+	struct acpi_subtable_header header;
+	u16 reserved;
+	u32 flags;
+	u32 next_level_of_cache;
+	u32 size;
+	u32 number_of_sets;
+	u8 associativity;
+	u8 attributes;
+	u16 line_size;
 	u32 cache_id;
 };
 
-- 
2.51.0

[PATCH v1 13/26] ACPICA: Fix asltests using the Fatal() opcode

[Rafael J. Wysocki]

From: Armin Wolf <W_Armin@gmx.de>

Some asltests test the behavior of the Fatal() opcode and thus require
that said opcode does not return an error when called.

Introduce a compile-time option called ACPI_CONTINUE_ON_FATAL to
instruct the executor to continue the execution of AML bytecode when
encountering a Fatal() opcode. Also update the asltest to use this
new option.

Fixes: ("Abort AML bytecode execution when executing AML_FATAL_OP")
Link: https://github.com/acpica/acpica/commit/428b3410c490
Signed-off-by: Armin Wolf <W_Armin@gmx.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpica/exoparg3.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/acpi/acpica/exoparg3.c b/drivers/acpi/acpica/exoparg3.c
index c8c8c4e49563..2fc8070814e3 100644
--- a/drivers/acpi/acpica/exoparg3.c
+++ b/drivers/acpi/acpica/exoparg3.c
@@ -72,11 +72,18 @@ acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
 
 		acpi_os_signal(ACPI_SIGNAL_FATAL, &fatal);
 
+#ifndef ACPI_CONTINUE_ON_FATAL
 		/*
 		 * Might return while OS is shutting down, so abort the AML execution
 		 * by returning an error.
 		 */
 		return_ACPI_STATUS(AE_ERROR);
+#else
+		/*
+		 * The alstests require that the Fatal() opcode does not return an error.
+		 */
+		return_ACPI_STATUS(AE_OK);
+#endif
 
 	case AML_EXTERNAL_OP:
 		/*
-- 
2.51.0

[PATCH v1 14/26] ACPICA: Add GICv5 MADT structures

[Rafael J. Wysocki]

From: Jose Marinho <jose.marinho@arm.com>

The GICv5 adds the following MADT structures:
 - IRS
 - ITS Config Frame
 - ITS Translate Frame

The ACPI spec ECR is at https://github.com/tianocore/edk2/issues/11148

Link: https://github.com/acpica/acpica/commit/69cca52ddf04
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl2.h | 49 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 45 insertions(+), 4 deletions(-)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 15856ae8b1e1..05ce897f1eeb 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -1294,7 +1294,10 @@ enum acpi_madt_type {
 	ACPI_MADT_TYPE_IMSIC = 25,
 	ACPI_MADT_TYPE_APLIC = 26,
 	ACPI_MADT_TYPE_PLIC = 27,
-	ACPI_MADT_TYPE_RESERVED = 28,	/* 28 to 0x7F are reserved */
+	ACPI_MADT_TYPE_GICV5_IRS = 28,
+	ACPI_MADT_TYPE_GICV5_ITS = 29,
+	ACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,
+	ACPI_MADT_TYPE_RESERVED = 31,	/* 31 to 0x7F are reserved */
 	ACPI_MADT_TYPE_OEM_RESERVED = 0x80	/* 0x80 to 0xFF are reserved for OEM use */
 };
 
@@ -1416,7 +1419,7 @@ struct acpi_madt_local_x2apic_nmi {
 	u8 reserved[3];		/* reserved - must be zero */
 };
 
-/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 changes) */
+/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 + ACPI 6.7 changes) */
 
 struct acpi_madt_generic_interrupt {
 	struct acpi_subtable_header header;
@@ -1437,6 +1440,8 @@ struct acpi_madt_generic_interrupt {
 	u8 reserved2[1];
 	u16 spe_interrupt;	/* ACPI 6.3 */
 	u16 trbe_interrupt;	/* ACPI 6.5 */
+	u16 iaffid;		/* ACPI 6.7 */
+	u32 irs_id;
 };
 
 /* Masks for Flags field above */
@@ -1459,7 +1464,7 @@ struct acpi_madt_generic_distributor {
 	u8 reserved2[3];	/* reserved - must be zero */
 };
 
-/* Values for Version field above */
+/* Values for Version field above and Version field in acpi_madt_gicv5_irs */
 
 enum acpi_madt_gic_version {
 	ACPI_MADT_GIC_VERSION_NONE = 0,
@@ -1467,7 +1472,8 @@ enum acpi_madt_gic_version {
 	ACPI_MADT_GIC_VERSION_V2 = 2,
 	ACPI_MADT_GIC_VERSION_V3 = 3,
 	ACPI_MADT_GIC_VERSION_V4 = 4,
-	ACPI_MADT_GIC_VERSION_RESERVED = 5	/* 5 and greater are reserved */
+	ACPI_MADT_GIC_VERSION_V5 = 5,
+	ACPI_MADT_GIC_VERSION_RESERVED = 6	/* 6 and greater are reserved */
 };
 
 /* 13: Generic MSI Frame (ACPI 5.1) */
@@ -1738,6 +1744,41 @@ struct acpi_madt_plic {
 	u32 gsi_base;
 };
 
+/* 28: Arm GICv5 IRS (ACPI 6.7) */
+struct acpi_madt_gicv5_irs {
+	struct acpi_subtable_header header;
+	u8 version;
+	u8 reserved;
+	u32 irs_id;
+	u32 flags;
+	u32 reserved2;
+	u64 config_base_address;
+	u64 setlpi_base_address;
+};
+
+#define ACPI_MADT_IRS_NON_COHERENT      (1)
+
+/* 29: Arm GICv5 ITS Config Frame (ACPI 6.7) */
+struct acpi_madt_gicv5_translator {
+	struct acpi_subtable_header header;
+	u8 flags;
+	u8 reserved;		/* reserved - must be zero */
+	u32 translator_id;
+	u64 base_address;
+};
+
+#define ACPI_MADT_GICV5_ITS_NON_COHERENT      (1)
+
+/* 30: Arm GICv5 ITS Translate Frame (ACPI 6.7) */
+struct acpi_madt_gicv5_translate_frame {
+	struct acpi_subtable_header header;
+	u16 reserved;		/* reserved - must be zero */
+	u32 linked_translator_id;
+	u32 translate_frame_id;
+	u32 reserved2;
+	u64 base_address;
+};
+
 /* 80: OEM data */
 
 struct acpi_madt_oem_data {
-- 
2.51.0

[PATCH v1 15/26] ACPICA: Add Arm IORT IWB node definitions

[Rafael J. Wysocki]

From: Jose Marinho <jose.marinho@arm.com>

The IORT IUWB node is defined in IORT issue E.g
See https://developer.arm.com/documentation/den0049/eg

Link: https://github.com/acpica/acpica/commit/a90dc2f5380c
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl2.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 05ce897f1eeb..01dc35e4b60a 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -682,6 +682,7 @@ enum acpi_iort_node_type {
 	ACPI_IORT_NODE_SMMU_V3 = 0x04,
 	ACPI_IORT_NODE_PMCG = 0x05,
 	ACPI_IORT_NODE_RMR = 0x06,
+	ACPI_IORT_NODE_IWB = 0x07,
 };
 
 struct acpi_iort_id_mapping {
@@ -860,6 +861,12 @@ struct acpi_iort_rmr_desc {
 	u32 reserved;
 };
 
+struct acpi_iort_iwb {
+	u64 base_address;
+	u16 iwb_index;		/* Unique IWB identifier matching with the IWB GSI namespace. */
+	char device_name[];	/* Path of the IWB namespace object */
+};
+
 /*******************************************************************************
  *
  * IOVT - I/O Virtualization Table
-- 
2.51.0

[PATCH v1 16/26] ACPICA: actbl2.h: ACPI 6.6: RAS2: Update Parameter Block structure

[Rafael J. Wysocki]

From: Pawel Chmielewski <pawel.chmielewski@intel.com>

ACPI 6.6 introduces RAS2 enhancements for patrol scrub functionality,
adding new fields to the Parameter Block structure. These fields are
applicable only in the response to the GET_PATROL_PARAMETERS command.

Link: https://github.com/acpica/acpica/commit/062842024000
Signed-off-by: Pawel Chmielewski <pawel.chmielewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl2.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 01dc35e4b60a..5c0b55e7b3e4 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -3249,6 +3249,8 @@ struct acpi_ras2_patrol_scrub_param {
 	u32 flags;
 	u32 scrub_params_out;
 	u32 scrub_params_in;
+	u32 ext_scrub_params;
+	u8 scrub_rate_desc[256];
 };
 
 /* Masks for Flags field above */
-- 
2.51.0

[PATCH v1 17/26] ACPICA: actbl3.h: ACPI 6.6: SRAT: New flag in Memory Affinity Structure

[Rafael J. Wysocki]

From: Pawel Chmielewski <pawel.chmielewski@intel.com>

ACPI 6.6 introduces Specific-Purpose flag to Memory Affinity structure.

Link: https://github.com/acpica/acpica/commit/cfce3b689b5e
Signed-off-by: Pawel Chmielewski <pawel.chmielewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl3.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/acpi/actbl3.h b/include/acpi/actbl3.h
index 79d3aa5a4bad..7ca456e88377 100644
--- a/include/acpi/actbl3.h
+++ b/include/acpi/actbl3.h
@@ -238,6 +238,7 @@ struct acpi_srat_mem_affinity {
 #define ACPI_SRAT_MEM_ENABLED       (1)	/* 00: Use affinity structure */
 #define ACPI_SRAT_MEM_HOT_PLUGGABLE (1<<1)	/* 01: Memory region is hot pluggable */
 #define ACPI_SRAT_MEM_NON_VOLATILE  (1<<2)	/* 02: Memory region is non-volatile */
+#define ACPI_SRAT_MEM_SPEC_PURPOSE  (1<<3)	/* 03: Memory is intended for specific-purpose usage */
 
 /* 2: Processor Local X2_APIC Affinity (ACPI 4.0) */
 
-- 
2.51.0

[PATCH v1 18/26] ACPICA: ACPI 6.6: Add _VDM (Voltage Domain) object

[Rafael J. Wysocki]

From: Pawel Chmielewski <pawel.chmielewski@intel.com>

A processor voltage domain is an identifier that specifies the voltage
plane associated with a given group of processors.

Refer to section 6.2.10. _VDM (Voltage Domain) of ACPI 6.6 specification
for more information.

Link: https://github.com/acpica/acpica/commit/d0dbb157646d
Signed-off-by: Pawel Chmielewski <pawel.chmielewski@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpica/acpredef.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/acpi/acpica/acpredef.h b/drivers/acpi/acpica/acpredef.h
index da2c45880cc7..5f70b196e0aa 100644
--- a/drivers/acpi/acpica/acpredef.h
+++ b/drivers/acpi/acpica/acpredef.h
@@ -587,6 +587,9 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Variable-length (Pkgs) each (var Ints) */
 	PACKAGE_INFO(ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5, 0, 0, 0),
 
+	{{"_VDM", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
+
 	{{"_HRV", METHOD_0ARGS,
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
 
-- 
2.51.0

[PATCH v1 19/26] ACPICA: Create auxiliary ACPI_TPR_AUX_SR structure for iASL compiler

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Define unofficial structure ACPI_TPR_AUX_SR, which holds information
about the number of serialization registers for TPRs.

It simplifies DTPR Serialization Request Info Table compilation.

Link: https://github.com/acpica/acpica/commit/31f470e708a9
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index f16020829f42..89541cd0c9b0 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -2001,6 +2001,11 @@ struct acpi_tpr_instance {
 	struct acpi_tpr_array tpr_array[];
 };
 
+struct acpi_tpr_aux_sr {
+	u32 srl_cnt;
+	//ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[];
+};
+
 /*******************************************************************************
  * TPRn_BASE
  *
-- 
2.51.0

[PATCH v1 20/26] ACPICA: Fix Segmentation Fault error related to DTPR

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Fix Segmentation Fault error, caused by invalid buffer lenght in DTPR
Table Template:

 * Update buffer length for TPR Table, which invalid value caused
   Segmentation Fault, during ASL file production.

 * Refactor invalid values of TPR instances, arrays and serialization
   requests count and TPR Base addresses in the DTPR table template.

 * Fix offset updating in the acpi_dm_dump_dtpr function.

Link: https://github.com/acpica/acpica/commit/f75850bc4717
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 89541cd0c9b0..59fbd64405be 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -2057,12 +2057,12 @@ struct acpi_tprn_limit_reg {
 *******************************************************************************/
 
 struct acpi_tpr_serialize_request {
-	u64 sts:1;		// status of serialization request (RO)
-	// 0 == register idle, 1 == serialization in progress
-	u64 ctrl:1;		// control field to initiate serialization (RW)
-	// 0 == normal, 1 == initialize serialization
+	u64 sr_register;
+	// BIT 1 - status of serialization request (RO)
+	//         0 == register idle, 1 == serialization in progress
+	// BIT 2 - control field to initiate serialization (RW)
+	//         0 == normal, 1 == initialize serialization
 	// (self-clear to allow multiple serialization requests)
-	u64 unused:62;
 };
 
 /* Reset to default packing */
-- 
2.51.0

[PATCH v1 21/26] ACPICA: Verify DTPR and TPR Instance buffer pointers

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Verify DTPR and TPR Instance buffer pointers and refactor comments.

Link: https://github.com/acpica/acpica/commit/bdec5b61cf5b
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 59 +++++++++++++++++++++++--------------------
 1 file changed, 32 insertions(+), 27 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 59fbd64405be..a580b993cc48 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -1987,7 +1987,7 @@ struct acpi_ibft_target {
 
 struct acpi_table_dtpr {
 	struct acpi_table_header header;
-	u32 flags;		// 36
+	u32 flags;		/* 36 */
 	u32 ins_cnt;
 };
 
@@ -2003,66 +2003,71 @@ struct acpi_tpr_instance {
 
 struct acpi_tpr_aux_sr {
 	u32 srl_cnt;
-	//ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[];
+	/* ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; */
 };
 
-/*******************************************************************************
+/*
  * TPRn_BASE
  *
  * Specifies the start address of TPRn region. TPR region address and size must
  * be with 1MB resolution. These bits are compared with the result of the
  * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an
  * access fall within the TPRn defined region.
-*******************************************************************************/
+ */
+
 struct acpi_tprn_base_reg {
 	u64 reserved0:3;
-	u64 rw:1;		// access: 1 == RO, 0 == RW (for TPR must be RW)
-	u64 enable:1;		// 0 == range enabled, 1 == range disabled
+	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
+	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
 	u64 reserved1:15;
-	u64 tpr_base_rw:44;	// minimal TPrn_base resolution is 1MB.
-	// applied to the incoming address, to determine if an
-	// access fall within the TPrn defined region.
-	// width is determined by a bus width which can be
-	// obtainedvia CPUID function 0x80000008.
-	//u64 unused : 1;
+	u64 tpr_base_rw:44;	/* Minimal TPRn_Base resolution is 1MB.
+				 *  Applied to the incoming address, to determine if
+				 *  an access fall within the TPRn defined region.
+				 *  Width is determined by a bus width which can be
+				 *  obtained via CPUID function 0x80000008.
+				 */
+	/* u64 unused : 1;   */
 };
 
-/*******************************************************************************
+/*
  * TPRn_LIMIT
  *
  * This register defines an isolated region of memory that can be enabled
  * to prohibit certain system agents from accessing memory. When an agent
  * sends a request upstream, whether snooped or not, a TPR prevents that
  * transaction from changing the state of memory.
-*******************************************************************************/
+ */
 
 struct acpi_tprn_limit_reg {
 	u64 reserved0:3;
-	u64 rw:1;		// access: 1 == RO, 0 == RW (for TPR must be RW)
-	u64 enable:1;		// 0 == range enabled, 1 == range disabled
+	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
+	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
 	u64 reserved1:15;
-	u64 tpr_limit_rw:44;	// minimal TPrn_limit resolution is 1MB.
-	// these bits define TPR limit address.
-	// width is determined by a bus width.
+	u64 tpr_limit_rw:44;	/* Minimal TPRn_Limit resolution is 1MB.
+				 *  These bits define TPR limit address.
+				 *  Width is determined by a bus width.
+				 */
 
-	//u64 unused : 1;
+	/* u64 unused : 1; */
 };
 
-/*******************************************************************************
+/*
  * SERIALIZE_REQUEST
  *
  * This register is used to request serialization of non-coherent DMA
  * transactions. OS shall  issue it before changing of TPR settings
  * (base / size).
-*******************************************************************************/
+ */
 
 struct acpi_tpr_serialize_request {
 	u64 sr_register;
-	// BIT 1 - status of serialization request (RO)
-	//         0 == register idle, 1 == serialization in progress
-	// BIT 2 - control field to initiate serialization (RW)
-	//         0 == normal, 1 == initialize serialization
-	// (self-clear to allow multiple serialization requests)
+	/*
+	 *  BIT 1 - Status of serialization request (RO)
+	 *          0 == register idle, 1 == serialization in progress
+	 *  BIT 2 - Control field to initiate serialization (RW)
+	 *          0 == normal, 1 == initialize serialization
+	 *  (self-clear to allow multiple serialization requests)
+	 */
 };
 
 /* Reset to default packing */
-- 
2.51.0

[PATCH v1 22/26] ACPICA: Cleanup comments and DTPR Table handle functions

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Link: https://github.com/acpica/acpica/commit/cc480264335e
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 35 ++++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index a580b993cc48..c5ff63fc3b72 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -2003,7 +2003,9 @@ struct acpi_tpr_instance {
 
 struct acpi_tpr_aux_sr {
 	u32 srl_cnt;
-	/* ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[]; */
+	/*
+	 * ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[];
+	 */
 };
 
 /*
@@ -2020,13 +2022,13 @@ struct acpi_tprn_base_reg {
 	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
 	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
 	u64 reserved1:15;
-	u64 tpr_base_rw:44;	/* Minimal TPRn_Base resolution is 1MB.
-				 *  Applied to the incoming address, to determine if
-				 *  an access fall within the TPRn defined region.
-				 *  Width is determined by a bus width which can be
-				 *  obtained via CPUID function 0x80000008.
+	u64 tpr_base_rw:44;	/*
+				 * Minimal TPRn_Base resolution is 1MB.
+				 * Applied to the incoming address, to determine if
+				 * an access fall within the TPRn defined region.
+				 * Width is determined by a bus width which can be
+				 * obtained via CPUID function 0x80000008.
 				 */
-	/* u64 unused : 1;   */
 };
 
 /*
@@ -2043,12 +2045,11 @@ struct acpi_tprn_limit_reg {
 	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
 	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
 	u64 reserved1:15;
-	u64 tpr_limit_rw:44;	/* Minimal TPRn_Limit resolution is 1MB.
-				 *  These bits define TPR limit address.
-				 *  Width is determined by a bus width.
+	u64 tpr_limit_rw:44;	/*
+				 * Minimal TPRn_Limit resolution is 1MB.
+				 * These bits define TPR limit address.
+				 * Width is determined by a bus width.
 				 */
-
-	/* u64 unused : 1; */
 };
 
 /*
@@ -2062,11 +2063,11 @@ struct acpi_tprn_limit_reg {
 struct acpi_tpr_serialize_request {
 	u64 sr_register;
 	/*
-	 *  BIT 1 - Status of serialization request (RO)
-	 *          0 == register idle, 1 == serialization in progress
-	 *  BIT 2 - Control field to initiate serialization (RW)
-	 *          0 == normal, 1 == initialize serialization
-	 *  (self-clear to allow multiple serialization requests)
+	 * BIT 1 - Status of serialization request (RO)
+	 *         0 == register idle, 1 == serialization in progress
+	 * BIT 2 - Control field to initiate serialization (RW)
+	 *         0 == normal, 1 == initialize serialization
+	 * (self-clear to allow multiple serialization requests)
 	 */
 };
 
-- 
2.51.0

[PATCH v1 23/26] ACPICA: Align comments in TPRn-related structures

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures.

Link: https://github.com/acpica/acpica/commit/95815d550969
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index c5ff63fc3b72..cdcda64d1d8e 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -1998,14 +1998,10 @@ struct acpi_tpr_array {
 struct acpi_tpr_instance {
 	u32 flags;
 	u32 tpr_cnt;
-	struct acpi_tpr_array tpr_array[];
 };
 
 struct acpi_tpr_aux_sr {
 	u32 srl_cnt;
-	/*
-	 * ACPI_TPR_SERIALIZE_REQUEST tpr_sr_arr[];
-	 */
 };
 
 /*
@@ -2022,13 +2018,14 @@ struct acpi_tprn_base_reg {
 	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
 	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
 	u64 reserved1:15;
-	u64 tpr_base_rw:44;	/*
-				 * Minimal TPRn_Base resolution is 1MB.
-				 * Applied to the incoming address, to determine if
-				 * an access fall within the TPRn defined region.
-				 * Width is determined by a bus width which can be
-				 * obtained via CPUID function 0x80000008.
-				 */
+	u64 tpr_base_rw:44;
+	/*
+	 * Minimal TPRn_Base resolution is 1MB.
+	 * Applied to the incoming address, to determine if
+	 * an access fall within the TPRn defined region.
+	 * Width is determined by a bus width which can be
+	 * obtained via CPUID function 0x80000008.
+	 */
 };
 
 /*
@@ -2045,11 +2042,12 @@ struct acpi_tprn_limit_reg {
 	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
 	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
 	u64 reserved1:15;
-	u64 tpr_limit_rw:44;	/*
-				 * Minimal TPRn_Limit resolution is 1MB.
-				 * These bits define TPR limit address.
-				 * Width is determined by a bus width.
-				 */
+	u64 tpr_limit_rw:44;
+	/*
+	 * Minimal TPRn_Limit resolution is 1MB.
+	 * These bits define TPR limit address.
+	 * Width is determined by a bus width.
+	 */
 };
 
 /*
-- 
2.51.0

[PATCH v1 24/26] ACPICA: Logfile: Changes for version 20251212

[Rafael J. Wysocki]

From: Saket Dumbre <saket.dumbre@intel.com>

Link: https://github.com/acpica/acpica/commit/446be438238e
Signed-off-by: Saket Dumbre <saket.dumbre@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/acpixf.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index e65a2afe9250..49d1749f30bb 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -12,7 +12,7 @@
 
 /* Current ACPICA subsystem version in YYYYMMDD format */
 
-#define ACPI_CA_VERSION                 0x20250807
+#define ACPI_CA_VERSION                 0x20251212
 
 #include <acpi/acconfig.h>
 #include <acpi/actypes.h>
-- 
2.51.0

[PATCH v1 25/26] ACPICA: Replace TPRn Base and Limit registers

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Replace TPRn Base and Limit registers with compatible bitmasks for them.

Link: https://github.com/acpica/acpica/commit/be91c5813936
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 99 +++++++++++++++++++++++++++++++------------
 1 file changed, 72 insertions(+), 27 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index cdcda64d1d8e..8331a3494b75 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -2005,28 +2005,57 @@ struct acpi_tpr_aux_sr {
 };
 
 /*
- * TPRn_BASE
+ * TPRn_BASE (ACPI_TPRN_BASE_REG)
  *
  * Specifies the start address of TPRn region. TPR region address and size must
  * be with 1MB resolution. These bits are compared with the result of the
  * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an
  * access fall within the TPRn defined region.
+ *
+ * Minimal TPRn_Base resolution is 1MB.
+ * Applied to the incoming address, to determine if
+ * an access fall within the TPRn defined region.
+ * Width is determined by a bus width which can be
+ * obtained via CPUID function 0x80000008.
  */
 
-struct acpi_tprn_base_reg {
-	u64 reserved0:3;
-	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
-	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
-	u64 reserved1:15;
-	u64 tpr_base_rw:44;
-	/*
-	 * Minimal TPRn_Base resolution is 1MB.
-	 * Applied to the incoming address, to determine if
-	 * an access fall within the TPRn defined region.
-	 * Width is determined by a bus width which can be
-	 * obtained via CPUID function 0x80000008.
-	 */
-};
+typedef u64 ACPI_TPRN_BASE_REG;
+
+/* TPRn_BASE Register Bit Masks */
+
+/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
+#define ACPI_TPRN_BASE_RW_SHIFT        3
+#define ACPI_TPRN_BASE_RW_MASK         ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT)
+
+/*
+ * Bit 4 - Enable: 0 – TPRn address range enabled;
+ *                 1 – TPRn address range disabled.
+ */
+#define ACPI_TPRN_BASE_ENABLE_SHIFT    4
+#define ACPI_TPRN_BASE_ENABLE_MASK     ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT)
+
+/* Bits 63:20 - tpr_base_rw */
+#define ACPI_TPRN_BASE_ADDR_SHIFT      20
+#define ACPI_TPRN_BASE_ADDR_MASK       ((u64) 0xFFFFFFFFFFF << \
+			 ACPI_TPRN_BASE_ADDR_SHIFT)
+
+/* TPRn_BASE Register Bit Handlers*/
+#define GET_TPRN_BASE_RW(reg)     (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >>  \
+					  ACPI_TPRN_BASE_RW_SHIFT)
+#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \
+							 >> ACPI_TPRN_BASE_ENABLE_SHIFT)
+#define GET_TPRN_BASE_ADDR(reg)   (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK)   \
+								   >> ACPI_TPRN_BASE_ADDR_SHIFT)
+
+#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,     \
+										ACPI_TPRN_BASE_RW_SHIFT,       \
+										ACPI_TPRN_BASE_RW_MASK, val);
+#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
+										ACPI_TPRN_BASE_ENABLE_SHIFT,   \
+										ACPI_TPRN_BASE_ENABLE_MASK, val);
+#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,   \
+										ACPI_TPRN_BASE_ADDR_SHIFT,     \
+										ACPI_TPRN_BASE_ADDR_MASK, val);
 
 /*
  * TPRn_LIMIT
@@ -2035,20 +2064,36 @@ struct acpi_tprn_base_reg {
  * to prohibit certain system agents from accessing memory. When an agent
  * sends a request upstream, whether snooped or not, a TPR prevents that
  * transaction from changing the state of memory.
+ *
+ * Minimal TPRn_Limit resolution is 1MB.
+ * Width is determined by a bus width
  */
 
-struct acpi_tprn_limit_reg {
-	u64 reserved0:3;
-	u64 rw:1;		/* access: 1 == RO, 0 == RW (for TPR must be RW) */
-	u64 enable:1;		/* 0 == range enabled, 1 == range disabled */
-	u64 reserved1:15;
-	u64 tpr_limit_rw:44;
-	/*
-	 * Minimal TPRn_Limit resolution is 1MB.
-	 * These bits define TPR limit address.
-	 * Width is determined by a bus width.
-	 */
-};
+typedef u64 ACPI_TPRN_LIMIT_REG;
+
+/* TPRn_LIMIT Register Bit Masks */
+
+/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
+#define ACPI_TPRN_LIMIT_RW_SHIFT   3
+#define ACPI_TPRN_LIMIT_RW_MASK    ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT)
+
+/* Bits 63:20 - tpr_limit_rw */
+#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20
+#define ACPI_TPRN_LIMIT_ADDR_MASK  ((u64) 0xFFFFFFFFFFF << \
+								   ACPI_TPRN_LIMIT_ADDR_SHIFT)
+
+/* TPRn_LIMIT Register Bit Handlers*/
+#define GET_TPRN_LIMIT_RW(reg)    (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK)    \
+								   >> ACPI_TPRN_LIMIT_RW_SHIFT)
+#define GET_TPRN_LIMIT_ADDR(reg)  (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK)  \
+								   >> ACPI_TPRN_LIMIT_ADDR_SHIFT)
+
+#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,            \
+										ACPI_TPRN_LIMIT_RW_SHIFT,              \
+										ACPI_TPRN_LIMIT_RW_MASK, val);
+#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,          \
+										ACPI_TPRN_LIMIT_ADDR_SHIFT,            \
+										ACPI_TPRN_LIMIT_ADDR_MASK, val);
 
 /*
  * SERIALIZE_REQUEST
-- 
2.51.0

[PATCH v1 26/26] ACPICA: Refactor for TPR Base/Limit registers bitmasks

[Rafael J. Wysocki]

From: Michal Camacho Romero <michal.camacho.romero@intel.com>

Link: https://github.com/acpica/acpica/commit/5cb62a1d4970
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 396 +++++++++++++++++++++++++++---------------
 1 file changed, 256 insertions(+), 140 deletions(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 8331a3494b75..4e15583e0d25 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -1000,6 +1000,262 @@ struct acpi_drtm_dps_id {
 	u8 dps_id[16];
 };
 
+/*******************************************************************************
+ *
+ * DTPR - DMA TXT Protection Ranges Table
+ *        Version 1
+ *
+ * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection
+ *              Ranges",
+ * Revision 0.73, August 2021
+ *
+ ******************************************************************************/
+
+struct acpi_table_dtpr {
+	struct acpi_table_header header;
+	u32 flags;		/* 36 */
+	u32 ins_cnt;
+};
+
+struct acpi_tpr_array {
+	u64 base;
+};
+
+struct acpi_tpr_instance {
+	u32 flags;
+	u32 tpr_cnt;
+};
+
+struct acpi_tpr_aux_sr {
+	u32 srl_cnt;
+};
+
+/*
+ * TPRn_BASE (ACPI_TPRN_BASE_REG)
+ *
+ * Specifies the start address of TPRn region. TPR region address and size must
+ * be with 1MB resolution. These bits are compared with the result of the
+ * TPRn_LIMIT[63:20], which is applied to the incoming address, to
+ * determine if an access fall within the TPRn defined region.
+ *
+ * Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to
+ * determine if an access fall within the TPRn defined region. Width is
+ * determined by a bus width which can be obtained via CPUID
+ * function 0x80000008.
+ */
+
+typedef u64 ACPI_TPRN_BASE_REG;
+
+/* TPRn_BASE Register Bit Masks */
+
+/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
+#define ACPI_TPRN_BASE_RW_SHIFT        3
+
+#define ACPI_TPRN_BASE_RW_MASK         ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT)
+
+/*
+ * Bit 4 - Enable: 0 – TPRn address range enabled;
+ *                 1 – TPRn address range disabled.
+ */
+#define ACPI_TPRN_BASE_ENABLE_SHIFT    4
+
+#define ACPI_TPRN_BASE_ENABLE_MASK     ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT)
+
+/* Bits 63:20 - tpr_base_rw */
+#define ACPI_TPRN_BASE_ADDR_SHIFT      20
+
+#define ACPI_TPRN_BASE_ADDR_MASK       ((u64) 0xFFFFFFFFFFF << \
+			 ACPI_TPRN_BASE_ADDR_SHIFT)
+
+/* TPRn_BASE Register Bit Handlers*/
+
+/*
+ * GET_TPRN_BASE_RW:
+ *
+ * Read RW bit from TPRn Base register - bit 3.
+ *
+ * Input:
+ * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
+ *
+ * Output:
+ *
+ * Returns RW bit value (u64).
+ */
+#define GET_TPRN_BASE_RW(reg)     (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >>  \
+					  ACPI_TPRN_BASE_RW_SHIFT)
+
+/*
+ * GET_TPRN_BASE_ENABLE:
+ *
+ * Read Enable bit from TPRn Base register - bit 4.
+ *
+ * Input:
+ * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
+ *
+ * Output:
+ *
+ * Returns Enable bit value (u64).
+ */
+#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \
+							 >> ACPI_TPRN_BASE_ENABLE_SHIFT)
+
+/*
+ * GET_TPRN_BASE_ADDR:
+ *
+ * Read TPRn Base Register address from bits 63:20.
+ *
+ * Input:
+ * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
+ *
+ * Output:
+ *
+ * Returns TPRn Base Register address (u64).
+ */
+#define GET_TPRN_BASE_ADDR(reg)   (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK)   \
+								   >> ACPI_TPRN_BASE_ADDR_SHIFT)
+
+/*
+ * SET_TPRN_BASE_RW:
+ *
+ * Set RW bit in TPRn Base register - bit 3.
+ *
+ * Input:
+ * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
+ * - val (represents RW value to be set (u64))
+ */
+#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,     \
+										ACPI_TPRN_BASE_RW_SHIFT,       \
+										ACPI_TPRN_BASE_RW_MASK, val);
+
+/*
+ * SET_TPRN_BASE_ENABLE:
+ *
+ * Set Enable bit in TPRn Base register - bit 4.
+ *
+ * Input:
+ * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
+ * - val (represents Enable value to be set (u64))
+ */
+#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
+										ACPI_TPRN_BASE_ENABLE_SHIFT,   \
+										ACPI_TPRN_BASE_ENABLE_MASK, val);
+
+/*
+ * SET_TPRN_BASE_ADDR:
+ *
+ * Set TPRn Base Register address - bits 63:20
+ *
+ * Input
+ * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
+ * - val (represents address value to be set (u64))
+ */
+#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,   \
+										ACPI_TPRN_BASE_ADDR_SHIFT,     \
+										ACPI_TPRN_BASE_ADDR_MASK, val);
+
+/*
+ * TPRn_LIMIT
+ *
+ * This register defines an isolated region of memory that can be enabled
+ * to prohibit certain system agents from accessing memory. When an agent
+ * sends a request upstream, whether snooped or not, a TPR prevents that
+ * transaction from changing the state of memory.
+ *
+ * Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width.
+ */
+
+typedef u64 ACPI_TPRN_LIMIT_REG;
+
+/* TPRn_LIMIT Register Bit Masks */
+
+/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
+#define ACPI_TPRN_LIMIT_RW_SHIFT   3
+
+#define ACPI_TPRN_LIMIT_RW_MASK    ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT)
+
+/* Bits 63:20 - tpr_limit_rw */
+#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20
+
+#define ACPI_TPRN_LIMIT_ADDR_MASK  ((u64) 0xFFFFFFFFFFF << \
+								   ACPI_TPRN_LIMIT_ADDR_SHIFT)
+
+/* TPRn_LIMIT Register Bit Handlers*/
+
+/*
+ * GET_TPRN_LIMIT_RW:
+ *
+ * Read RW bit from TPRn Limit register - bit 3.
+ *
+ * Input:
+ * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
+ *
+ * Output:
+ *
+ * Returns RW bit value (u64).
+ */
+#define GET_TPRN_LIMIT_RW(reg)    (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK)    \
+								   >> ACPI_TPRN_LIMIT_RW_SHIFT)
+
+/*
+ * GET_TPRN_LIMIT_ADDR:
+ *
+ * Read TPRn Limit Register address from bits 63:20.
+ *
+ * Input:
+ * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
+ *
+ * Output:
+ *
+ * Returns TPRn Limit Register address (u64).
+ */
+#define GET_TPRN_LIMIT_ADDR(reg)  (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK)  \
+								   >> ACPI_TPRN_LIMIT_ADDR_SHIFT)
+
+/*
+ * SET_TPRN_LIMIT_RW:
+ *
+ * Set RW bit in TPRn Limit register - bit 3.
+ *
+ * Input:
+ * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
+ * - val (represents RW value to be set (u64))
+ */
+#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,            \
+										ACPI_TPRN_LIMIT_RW_SHIFT,              \
+										ACPI_TPRN_LIMIT_RW_MASK, val);
+
+/*
+ * SET_TPRN_LIMIT_ADDR:
+ *
+ * Set TPRn Limit Register address - bits 63:20.
+ *
+ * Input:
+ * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
+ * - val (represents address value to be set (u64))
+ */
+#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,          \
+										ACPI_TPRN_LIMIT_ADDR_SHIFT,            \
+										ACPI_TPRN_LIMIT_ADDR_MASK, val);
+
+/*
+ * SERIALIZE_REQUEST
+ *
+ * This register is used to request serialization of non-coherent DMA
+ * transactions. OS shall  issue it before changing of TPR settings
+ * (base / size).
+ */
+
+struct acpi_tpr_serialize_request {
+	u64 sr_register;
+	/*
+	 * BIT 1 - Status of serialization request (RO)
+	 *         0 == register idle, 1 == serialization in progress
+	 * BIT 2 - Control field to initiate serialization (RW)
+	 *         0 == normal, 1 == initialize serialization
+	 * (self-clear to allow multiple serialization requests)
+	 */
+};
+
 /*******************************************************************************
  *
  * ECDT - Embedded Controller Boot Resources Table
@@ -1974,146 +2230,6 @@ struct acpi_ibft_target {
 	u16 reverse_chap_secret_offset;
 };
 
-/*******************************************************************************
- *
- * DTPR - DMA TXT Protection Ranges Table
- *        Version 1
- *
- * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection
- *              Ranges",
- * Revision 0.73, August 2021
- *
- ******************************************************************************/
-
-struct acpi_table_dtpr {
-	struct acpi_table_header header;
-	u32 flags;		/* 36 */
-	u32 ins_cnt;
-};
-
-struct acpi_tpr_array {
-	u64 base;
-};
-
-struct acpi_tpr_instance {
-	u32 flags;
-	u32 tpr_cnt;
-};
-
-struct acpi_tpr_aux_sr {
-	u32 srl_cnt;
-};
-
-/*
- * TPRn_BASE (ACPI_TPRN_BASE_REG)
- *
- * Specifies the start address of TPRn region. TPR region address and size must
- * be with 1MB resolution. These bits are compared with the result of the
- * TPRn_LIMIT[63:20] * applied to the incoming address, to determine if an
- * access fall within the TPRn defined region.
- *
- * Minimal TPRn_Base resolution is 1MB.
- * Applied to the incoming address, to determine if
- * an access fall within the TPRn defined region.
- * Width is determined by a bus width which can be
- * obtained via CPUID function 0x80000008.
- */
-
-typedef u64 ACPI_TPRN_BASE_REG;
-
-/* TPRn_BASE Register Bit Masks */
-
-/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
-#define ACPI_TPRN_BASE_RW_SHIFT        3
-#define ACPI_TPRN_BASE_RW_MASK         ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT)
-
-/*
- * Bit 4 - Enable: 0 – TPRn address range enabled;
- *                 1 – TPRn address range disabled.
- */
-#define ACPI_TPRN_BASE_ENABLE_SHIFT    4
-#define ACPI_TPRN_BASE_ENABLE_MASK     ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT)
-
-/* Bits 63:20 - tpr_base_rw */
-#define ACPI_TPRN_BASE_ADDR_SHIFT      20
-#define ACPI_TPRN_BASE_ADDR_MASK       ((u64) 0xFFFFFFFFFFF << \
-			 ACPI_TPRN_BASE_ADDR_SHIFT)
-
-/* TPRn_BASE Register Bit Handlers*/
-#define GET_TPRN_BASE_RW(reg)     (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >>  \
-					  ACPI_TPRN_BASE_RW_SHIFT)
-#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \
-							 >> ACPI_TPRN_BASE_ENABLE_SHIFT)
-#define GET_TPRN_BASE_ADDR(reg)   (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK)   \
-								   >> ACPI_TPRN_BASE_ADDR_SHIFT)
-
-#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,     \
-										ACPI_TPRN_BASE_RW_SHIFT,       \
-										ACPI_TPRN_BASE_RW_MASK, val);
-#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
-										ACPI_TPRN_BASE_ENABLE_SHIFT,   \
-										ACPI_TPRN_BASE_ENABLE_MASK, val);
-#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,   \
-										ACPI_TPRN_BASE_ADDR_SHIFT,     \
-										ACPI_TPRN_BASE_ADDR_MASK, val);
-
-/*
- * TPRn_LIMIT
- *
- * This register defines an isolated region of memory that can be enabled
- * to prohibit certain system agents from accessing memory. When an agent
- * sends a request upstream, whether snooped or not, a TPR prevents that
- * transaction from changing the state of memory.
- *
- * Minimal TPRn_Limit resolution is 1MB.
- * Width is determined by a bus width
- */
-
-typedef u64 ACPI_TPRN_LIMIT_REG;
-
-/* TPRn_LIMIT Register Bit Masks */
-
-/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
-#define ACPI_TPRN_LIMIT_RW_SHIFT   3
-#define ACPI_TPRN_LIMIT_RW_MASK    ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT)
-
-/* Bits 63:20 - tpr_limit_rw */
-#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20
-#define ACPI_TPRN_LIMIT_ADDR_MASK  ((u64) 0xFFFFFFFFFFF << \
-								   ACPI_TPRN_LIMIT_ADDR_SHIFT)
-
-/* TPRn_LIMIT Register Bit Handlers*/
-#define GET_TPRN_LIMIT_RW(reg)    (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK)    \
-								   >> ACPI_TPRN_LIMIT_RW_SHIFT)
-#define GET_TPRN_LIMIT_ADDR(reg)  (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK)  \
-								   >> ACPI_TPRN_LIMIT_ADDR_SHIFT)
-
-#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,            \
-										ACPI_TPRN_LIMIT_RW_SHIFT,              \
-										ACPI_TPRN_LIMIT_RW_MASK, val);
-#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg,          \
-										ACPI_TPRN_LIMIT_ADDR_SHIFT,            \
-										ACPI_TPRN_LIMIT_ADDR_MASK, val);
-
-/*
- * SERIALIZE_REQUEST
- *
- * This register is used to request serialization of non-coherent DMA
- * transactions. OS shall  issue it before changing of TPR settings
- * (base / size).
- */
-
-struct acpi_tpr_serialize_request {
-	u64 sr_register;
-	/*
-	 * BIT 1 - Status of serialization request (RO)
-	 *         0 == register idle, 1 == serialization in progress
-	 * BIT 2 - Control field to initiate serialization (RW)
-	 *         0 == normal, 1 == initialize serialization
-	 * (self-clear to allow multiple serialization requests)
-	 */
-};
-
 /* Reset to default packing */
 
 #pragma pack()
-- 
2.51.0