From: Nate Lawson <nate-Y6VGUYTwhu0@public.gmane.org>
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
Cc: Paul Diefenbaugh
<paul.s.diefenbaugh-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Subject: dummy read after reading p_lvl2?
Date: Sun, 5 Oct 2003 11:21:51 -0700 (PDT) [thread overview]
Message-ID: <20031005111720.P474@root.org> (raw)
I noticed that the processor.c driver does a dummy read of the xtimer
register after a read of p_lvl2 or p_lvl3. Why is this? Is there some
kind of delay slot that is never executed? The spec is very thin on this
area. Also, how long does it take to enter level 2 or 3 after the read
from the p_lvlX register? The spec says on the same clock cycle but I
wonder if it means cpu clock or acpi timer clock.
I've written a Cx driver for FreeBSD and it appears to work although I
need to measure power consumption to be sure.
Thanks,
Nate
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reply other threads:[~2003-10-05 18:21 UTC|newest]
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