From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nate Lawson Subject: dummy read after reading p_lvl2? Date: Sun, 5 Oct 2003 11:21:51 -0700 (PDT) Sender: acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Message-ID: <20031005111720.P474@root.org> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-path: Errors-To: acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Help: List-Post: List-Subscribe: , List-Unsubscribe: , List-Archive: To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Cc: Paul Diefenbaugh List-Id: linux-acpi@vger.kernel.org I noticed that the processor.c driver does a dummy read of the xtimer register after a read of p_lvl2 or p_lvl3. Why is this? Is there some kind of delay slot that is never executed? The spec is very thin on this area. Also, how long does it take to enter level 2 or 3 after the read from the p_lvlX register? The spec says on the same clock cycle but I wonder if it means cpu clock or acpi timer clock. I've written a Cx driver for FreeBSD and it appears to work although I need to measure power consumption to be sure. Thanks, Nate ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf