Via 694X based SMB boards (Apollo Pro133A)

Via 694X based SMB boards (Apollo Pro133A)

[Dino Klein]

Hello everybody,

I'm playing around with my Abit VP6 board - trying to get it into S3, and monkeying around with the Cx states.
I'm having a problem figuring out how the Via VT82C686B chipset works with two processors, since a datasheet I found for it
specifies only one P_BLK. Perhaps I have an older datasheet...

Anyway, unless someone tells me that a the Apollo Pro133A chipset doesn't properly support SMP, I would like to ask other people out
there who have 694X(DP) SMP board to take a look at their DSDT and send me the lines containing the processors definitions. If you
don't know how to find it, just send me the whole thing, and I'll figure it out; maybe this way I'll figure out the address of the
other P_BLK.

Thanks.


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Nate Lawson]

On Thu, 15 Jan 2004, Dino Klein wrote:
> I'm playing around with my Abit VP6 board - trying to get it into S3, and monkeying around with the Cx states.
> I'm having a problem figuring out how the Via VT82C686B chipset works with two processors, since a datasheet I found for it
> specifies only one P_BLK. Perhaps I have an older datasheet...
>
> Anyway, unless someone tells me that a the Apollo Pro133A chipset doesn't properly support SMP, I would like to ask other people out
> there who have 694X(DP) SMP board to take a look at their DSDT and send me the lines containing the processors definitions. If you
> don't know how to find it, just send me the whole thing, and I'll figure it out; maybe this way I'll figure out the address of the
> other P_BLK.

If you're looking to do throttling, some SMP boards support it.  The most
common way is with a shared P_BLK.  Either both Processor objects in the
ASL will have the same P_BLK or one will have it and the other will have a
NULL entry.  Either way, setting throttling through the P_BLK _ONCE_ (not
once per processor) sets the throttling level.

I've never seen an SMP board with separate P_BLKs per processor.  I've
also never seen an SMP board that supported C2 or higher via a shared
P_LVL2 register or separate _CST objects if it had different per-processor
P_LVL2 registers.  If anyone is aware of one of these, I'm very
interested.

-Nate


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Dino Klein]

> If you're looking to do throttling, some SMP boards support it.  The most
> common way is with a shared P_BLK.  Either both Processor objects in the
> ASL will have the same P_BLK or one will have it and the other will have a
> NULL entry.  Either way, setting throttling through the P_BLK _ONCE_ (not
> once per processor) sets the throttling level.


Actually, I did play with the throttling, but not through the ACPI driver. I wrote directly to the register, and the system was
reduced to  ~5% (according to the datasheets) of it's former glory. I did that with both CPUs on the board, which makes me wonder -
is there some way to figure out what is the clock speed of a particular CPU? maybe this way I can figure out whether my actions
operate on both CPUs or only one one.


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Ian Pilcher]

Dino Klein wrote:
> Hello everybody,
> 
> I'm playing around with my Abit VP6 board - trying to get it into S3, and monkeying around with the Cx states.
> I'm having a problem figuring out how the Via VT82C686B chipset works with two processors, since a datasheet I found for it
> specifies only one P_BLK. Perhaps I have an older datasheet...
> 
> Anyway, unless someone tells me that a the Apollo Pro133A chipset doesn't properly support SMP, I would like to ask other people out
> there who have 694X(DP) SMP board to take a look at their DSDT and send me the lines containing the processors definitions. If you
> don't know how to find it, just send me the whole thing, and I'll figure it out; maybe this way I'll figure out the address of the
> other P_BLK.
> 

I'll be glad to help any way I can.  You may want to see the "Plea for
help" thread, to see some problems that ACPI exposes on my VP6.

How do I extract/interpret the DSDT?

-- 
========================================================================
Ian Pilcher                                        i.pilcher-Wuw85uim5zDR7s880joybQ@public.gmane.org
========================================================================



-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Dino Klein]

> I'll be glad to help any way I can.  You may want to see the "Plea for
> help" thread, to see some problems that ACPI exposes on my VP6.

Sorry, I missed that one. Can you forward me a private copy, so I can see if I can contribute, without flooding everybody else. I'd
check the archive, but SourceForge seems to be in bad shape.

> How do I extract/interpret the DSDT?

Well, since we have the same board there isn't any point in checking. I'm interested in seeing the DSDT from motherboards by other
manufacturers. Other than that, the compiled DSDT is found at "/proc/acpi/dsdt". You can use Intel's compiler to disassemble it;
check the download section at http://acpi.sf.net for the link.


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Nate Lawson]

On Thu, 15 Jan 2004, Dino Klein wrote:
> > If you're looking to do throttling, some SMP boards support it.  The most
> > common way is with a shared P_BLK.  Either both Processor objects in the
> > ASL will have the same P_BLK or one will have it and the other will have a
> > NULL entry.  Either way, setting throttling through the P_BLK _ONCE_ (not
> > once per processor) sets the throttling level.
>
> Actually, I did play with the throttling, but not through the ACPI
> driver. I wrote directly to the register, and the system was reduced to
> ~5% (according to the datasheets) of it's former glory. I did that with
> both CPUs on the board, which makes me wonder - is there some way to
> figure out what is the clock speed of a particular CPU? maybe this way I
> can figure out whether my actions operate on both CPUs or only one one.

What are your Processor objects?  Here's a dual processor Xeon board with
a duplicated P_BLK.  The extra two objects are for the hyperthreading
logical CPUs.

IntelSE7501BR2.asl:        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
IntelSE7501BR2.asl:        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
IntelSE7501BR2.asl:        Processor (CPU3, 0x06, 0x00000410, 0x06) {}
IntelSE7501BR2.asl:        Processor (CPU4, 0x07, 0x00000410, 0x06) {}

No idea how to check clock speed of a particular CPU.  Try running a
benchmark pinned to one CPU and then the other.  I don't know the Linux
command for setting CPU affinity.  You could also run two tasks in
parallel that are a CPU benchmark.  Since throttling is linear, if you set
50% throttling and you get both tasks taking twice the time with
throttling as without, both CPUs are throttled.  If both tasks finish in
25% of the time, one processor is not throttled.

-Nate


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Nate Lawson]

On Fri, 16 Jan 2004, Dino Klein wrote:
> > What are your Processor objects?  Here's a dual processor Xeon board with
> > a duplicated P_BLK.  The extra two objects are for the hyperthreading
> > logical CPUs.
> >
> > IntelSE7501BR2.asl:        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
> > IntelSE7501BR2.asl:        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
> > IntelSE7501BR2.asl:        Processor (CPU3, 0x06, 0x00000410, 0x06) {}
> > IntelSE7501BR2.asl:        Processor (CPU4, 0x07, 0x00000410, 0x06) {}
>
> For my motherboard there is no P_BLK specified for either CPU.
> However, what you show here makes me wonder about this:
> ******
> 4.7.3.5 Processor Register Block (P_BLK)
> This optional register block is used to control each processor in the
> system. There is one unique processor register block per processor in the
> system.
> ******
>
> This is from the 2.0c spec, which also appears in 1.0b.
> Doesn't this imply that the statistics collected regarding the number of
> state promotions/demotions are meanigless?

Can't parse your question.  Without a P_BLK, you shouldn't be doing ACPI
throttling.  I assume you guessed at the P_BLK address or hardcoded it
from a datasheet?

-Nate


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Dino Klein]

> What are your Processor objects?  Here's a dual processor Xeon board with
> a duplicated P_BLK.  The extra two objects are for the hyperthreading
> logical CPUs.
>
> IntelSE7501BR2.asl:        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
> IntelSE7501BR2.asl:        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
> IntelSE7501BR2.asl:        Processor (CPU3, 0x06, 0x00000410, 0x06) {}
> IntelSE7501BR2.asl:        Processor (CPU4, 0x07, 0x00000410, 0x06) {}

For my motherboard there is no P_BLK specified for either CPU.
However, what you show here makes me wonder about this:
******
4.7.3.5 Processor Register Block (P_BLK)
This optional register block is used to control each processor in the
system. There is one unique processor register block per processor in the
system.
******

This is from the 2.0c spec, which also appears in 1.0b.
Doesn't this imply that the statistics collected regarding the number of
state promotions/demotions are meanigless?
Perhaps I'm missing something, but that's how I understand it. Nevertheless,
I will give this scheme a try, just for the hell of it.


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn

Re: Via 694X based SMB boards (Apollo Pro133A)

[Dino Klein]

> Can't parse your question.  Without a P_BLK, you shouldn't be doing ACPI
> throttling.  I assume you guessed at the P_BLK address or hardcoded it
> from a datasheet?

That's right (I did  mention that two emails back). I got the P_BLK from the
datasheet, and added it to the DSDT; however, in order to use throttling I
wrote a small program to write directly to the register since the DUTY_WIDTH
is wrong.


-------------------------------------------------------
The SF.Net email is sponsored by EclipseCon 2004
Premiere Conference on Open Tools Development and Integration
See the breadth of Eclipse activity. February 3-5 in Anaheim, CA.
http://www.eclipsecon.org/osdn