Re: Entering C3 Processor State without a Bus Arbiter

[Nate Lawson <nate-Y6VGUYTwhu0@public.gmane.org>]

On Fri, 16 Jan 2004, Dominik Brodowski wrote:
> On Thu, Jan 15, 2004 at 03:52:12PM -0800, Nate Lawson wrote:
> > > After removing the restrictions in the source files, and adding a WBINVD
> > > instruction right before the read from P_LVL3 - the processor was put in
> > > the C3 state. This is on my Via Apollo Pro133A based Abit VP6 board,
> > > which does not have a Bus Arbiter. Just for the record, I did pull out
> > > the second CPU, so I can do "safer" experimentation.
> >
> > WBINVD is too expensive when you're entering C3 hundreds of times per
> > second.  Try playing back an mp3 while dd'ing a CDROM in PIO mode to your
> > hard drive.  Goodbye data, hello backups!  The CPU can't snoop the bus in
> > C3.
>
> You shouldn't enter C3 at all when the CPU is woken up hundreds of times per
> second. Maximum allowed latency is 1ms, IIRC -- you really shouldn't get
> into this state while dd'ing a CDROM or something else...
>
> Problem is, WBINVD might take even longer than 1ms, even though the maximum
> I got on my PIII notebook was about 900us...

The processor code in Linux degrades to C2 when the last sleep was less
than its latency.  So if you have 900 us C3 latency, you can be woken up a
thousand times a second without degrading to C2.

The other, more important point I was trying to make is that without a BM
control, he won't get awoken for BM events and there will be DMA
underruns.  The issue with C3 is both latency and BM events.

-Nate


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